Abstract: A data length detection device for detecting the byte length of received data in accordance with High Level Data Link Control Procedure is disclosed. When the byte length of an information field included in the received data, for example, is detected, initial data determined based on the byte length is generated from initial data generation circuit. A counting device, after being initialized by the initial data, starts counting operation in response to detection of a start flag. When a stop flat is detected, the counting device stops the counting operation, and the data counted at the time represents the byte length of the information field. Since an adder/subtracter is not necessary to detect the byte length, time required for the detection can be shortened.

Abstract: An output circuit is disclosed for a semiconductor integrated circuit, having a controllable load drive capability. In a training mode for setting a load drive capability, a comparator compares the output signal generated from a driver circuit with the externally designated reference voltage. The control circuit controls the load drive capability of the driver circuit in response to the result of the comparison. The load drive capability of driver circuit 2 is set to a desired value by repeating the processing for these comparison and control. Accordingly, by externally controlling the level of the reference voltage, an output buffer can be obtained which is capable of setting the load drive capability to any value.

Abstract: An improved ring oscillator is disclosed which can be formed in a semiconductor substrate. The ring oscillator includes inverters cascaded in a ring-like manner, and a diffused resistor R1 having a positive temperature coefficient and a polysilicon resistor R2 having a negative temperature coefficient for determining bias currents supplied to the inverters. The oscillation frequency tends to decrease with a rise of ambient temperature based on a temperature characteristic of diffused resistor R1 and a temperature characteristic of the oscillator circuit itself; however, the change of oscillation frequency is compensated by a temperature characteristic of polysilicon resistor R2. Therefore, a reference clock signal generating circuit having an oscillation frequency which is not affected by change of the ambient temperature can be formed in the semiconductor substrate.

Abstract: A signal generator for generating pulse signals having a waveform required by the Recommendation of International Telegraph and Telephone Consultative Committee (CCITT) is disclosed. The signal generator utilizes two D/A converters whereby the limitation of the operable frequency of the D/A converters restricts the variation rate of the output pulses. Each D/A converter provides the converted analog signal to the pulse transformer at timings different from one another. The pulse transformer detects the difference between the provided analog signals and provides a pulse signal having the required waveform. The difference of the output voltages between the two D/A converters varies at two times the operable frequency rate of the D/A converters, resulting in the pulse signals changing at a rate exceeding the operation frequency of the D/A converters.

Abstract: A reference voltage generating circuit (9) for supplying a reference voltage (Vag.+-..DELTA.V) is connected to a peak hold or tracking circuit (34). The setting value of the voltage (.DELTA.V) is determined to a value exceeding the minute voltage fluctuations, such as back pulses or noises, occasionally contained in the input signal (Vin), by the voltage division in the generating circuit (9). Therefore, in response to the input signal Vin in accordance with the alternate mark inversion, exact data which is not influenced by the minute voltage fluctuation can be detected by the data detector (33).

Abstract: A D/A converter utilizing a redundant binary expression includes a current supplying circuit and a current decreasing circuit operating responsive to each bit in the signal expressed in the redundant binary expression. The current supply circuit and the current decreasing circuit have their outputs connected together while their current driving capacities are established in response to the functions of the powers of 2 for each bit. In this manner, this D/A converter is able to convert the data signals expressed in the binary redundant expression directly into analog signals.

Abstract: An input circuit provided in a MOS semiconductor IC having a compatible characteristics with an external TTL circuit. The input circuit comprises a circuit for generating a fixed reference voltage without depending on any supplied source voltage level, and a circuit for comparing the input voltage with the reference voltage. Therefore, a fixed margin for detecting the logic value of the input signal can be ensured regardless of whether the source voltage supplied is either 3.0 volts or 5.0 volts.