Patents by Inventor Hasan Sharifi

Hasan Sharifi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9466746
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 11, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Patent number: 9444001
    Abstract: A position sensitive detector includes a substrate, an absorber layer on the substrate, a barrier layer on the absorber layer, a contact layer on the barrier layer, and a first contact and a second contact on the contact layer. The barrier layer prevents a flow of majority carriers from the absorber layer to the contact layer. The position sensitive detector is sensitive to a lateral position between the first contact and the second contact of incident light on the contact layer.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 13, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Hasan Sharifi, Rajesh D. Rajavel, Terence J. De Lyon, Daniel Yap
  • Publication number: 20160149558
    Abstract: A multi-port active circulator where each of plurality of FET transistors has (i) a gate connected to an associated port of the multi-port active circulator via a capacitor of an associated one of a plurality of first RF chokes, each of the first RF chokes being connected to a gate of an associated FET transistor of said plurality of transistors, the associated port of said associated FET transistor and to a power supply bias connection; (ii) a source connected to a common point; and (iii) a drain connected to the gate of the same FET transistor by a feedback circuit and connected to the gate of a neighboring FET transistor via a capacitor of one of a plurality of second RF chokes, each of which coupling gates and drains of neighboring FET transistors via capacitors thereof and being connected to another power supply bias connection.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Applicant: HRL Laboratories, LLC
    Inventors: Jongchan KANG, Hasan SHARIFI, Eric M. PROPHET
  • Patent number: 9293612
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: March 22, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Patent number: 9231137
    Abstract: Using a highly doped Cap layer of the same composition as the Contact material in an nBn or pBp infrared photodetector allows engineering of the energy band diagram to facilitate minority carrier current flow in the contact region and block minority current flow outside the Contact region. The heavily doped Cap layer is disposed on the Barrier between the Contacts but electrically isolated from the Contact material.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: January 5, 2016
    Assignee: HRL Laboratories, LLC
    Inventors: Hasan Sharifi, Terence J. De Lyon, Rajesh D. Rajavel
  • Patent number: 9146157
    Abstract: A dual band detector includes a substrate, a composite barrier, a first absorber on the substrate and on a light incident side of the composite barrier, the first absorber for detecting first infrared light wavelengths, a second absorber on the composite barrier on a side opposite the light incident side, the second absorber for detecting second infrared light wavelengths, wherein a bandgap of the first absorber is larger than that of the second absorber, wherein the composite barrier includes a first secondary barrier, a primary barrier, and a second secondary barrier, wherein the first and second secondary barriers may have a lower bandgap energy than the primary barrier, wherein the first or the second secondary barrier may have a doping level and type different from that of the primary barrier, and wherein at least the primary barrier blocks majority carriers and allows minority carrier flow.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: September 29, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh Rajavel, Hasan Sharifi, Terence De Lyon, Brett Nosho, Daniel Yap
  • Patent number: 9103914
    Abstract: Optical angle of arrival sensors and methods for determining an angle of arrival of incident light are provided, wherein one sensor includes a focusing lens and an array of lateral-effect position sensing detector (LEPSD) elements. The focusing lens is configured to focus light on the array, wherein each of the LEPSD elements includes an absorber region that absorbs light of a first wavelength range that is focused on the LEPSD elements. Each of the LEPSD elements further includes at least one lateral current conducting layer that has a relatively low sheet resistance.
    Type: Grant
    Filed: December 21, 2013
    Date of Patent: August 11, 2015
    Assignee: The Boeing Company
    Inventors: Daniel Yap, Donald A. Hitko, Hasan Sharifi, Oleg M. Efimov
  • Patent number: 9087854
    Abstract: A method of three dimensional heterogeneous integration including forming HBT devices on a first substrate, each HBT device having a collector, removing the first substrate, forming first bonding pads on each collector of the heterojunction bipolar transistor devices, forming high electron mobility transistor (HEMT) devices on a first side of a growth substrate, wherein the growth substrate comprises a thermally conductive substrate, such as SiC or diamond, forming second bonding pads on the first side of the growth substrate, aligning and bonding the first bonding pads to the second bonding pads, forming CMOS devices on a Si substrate, bonding the CMOS devices on the Si substrate to a second side of the growth substrate, and forming selectively interconnects between the HBT devices, the HEMT devices, and the CMOS devices by forming vias and first and second level metal interconnects.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: July 21, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Wonill Ha, Hasan Sharifi, Tahir Hussain, James Chingwei Li, Pamela R. Patterson
  • Publication number: 20150177381
    Abstract: Optical angle of arrival sensors and methods for determining an angle of arrival of incident light are provided, wherein one sensor includes a focusing lens and an array of lateral-effect position sensing detector (LEPSD) elements. The focusing lens is configured to focus light on the array, wherein each of the LEPSD elements includes an absorber region that absorbs light of a first wavelength range that is focused on the LEPSD elements. Each of the LEPSD elements further includes at least one lateral current conducting layer that has a relatively low sheet resistance.
    Type: Application
    Filed: December 21, 2013
    Publication date: June 25, 2015
    Applicant: The Boeing Company
    Inventors: Daniel Yap, Donald A. Hitko, Hasan Sharifi, Oleg M. Efimov
  • Patent number: 9064992
    Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: June 23, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Brett Z Nosho, Rajesh D Rajavel, Hasan Sharifi, Sevag Terterian
  • Patent number: 8969986
    Abstract: An infrared photo-detector with multiple discrete regions of a first absorber material. These regions may have geometric shapes with sloped sidewalls. The detector also may include a second absorber region comprising a second absorber material that absorbs light of a shorter wavelength than the light absorbed by the multiple discrete absorber regions of the first absorber material. The geometric shapes may extend only through the first absorber material. Alternatively, the geometric shapes may extend partially into the second absorber region. The detector has a metal reflector coupled to the multiple discrete absorber regions. The detector also has a substrate containing the discrete absorber regions and the second absorber region. The substrate can further include geometric shaped features etched into the substrate, with those features formed on the side of the substrate opposite the side containing the discrete absorber regions and the second absorber region.
    Type: Grant
    Filed: February 28, 2011
    Date of Patent: March 3, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Daniel Yap, Rajesh D. Rajavel, Sarabjit Mehta, Hasan Sharifi
  • Patent number: 8847202
    Abstract: A dual-band infrared detector structure based on Type-II superlattices (T2SL) has been developed and experimentally validated. The structure according to the principles of the present invention is designed for a single Indium bump architecture and utilizes a T2SL barrier design that omits the traditional p-n junction region. The barrier design comprises multiple periods where each period comprises multiple monolayers doped P type. By selecting the composition, number of monolayers per period and number of periods, a transition region is created in the conduction band between a first absorber layer and a second absorber layer that allows operation at low biases (<100 mV for both bands) and exhibits a dark current density in the longer wavelength band comparable to that obtained with single-color detectors.
    Type: Grant
    Filed: January 17, 2012
    Date of Patent: September 30, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Brett Z. Nosho, Rajesh D. Rajavel, Hasan Sharifi, Sevag Terterian
  • Patent number: 8835979
    Abstract: Using a multiple layer, varied composition barrier layer in place of the typical single layer barrier layer of an infrared photodetector results in a device with increased sensitivity and reduced dark current. A first barrier is adjacent the semiconductor contact; a second barrier layer is between the first barrier layer and the absorber layer. The barrier layers may be doped N type or P type with Beryllium, Carbon, Silicon or Tellurium. The energy bandgap is designed to facilitate minority carrier current flow in the contact region and block minority current flow outside the contact region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 16, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Terence J De Lyon, Rajesh D Rajavel, Hasan Sharifi
  • Patent number: 8592983
    Abstract: A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: November 26, 2013
    Assignee: The Boeing Company
    Inventors: Hasan Sharifi, Alexandros D. Margomenos, Ara K. Kurdoghlian, Miroslav Micovic, Keisuke Shinohara, Colleen M. Butler
  • Publication number: 20130140579
    Abstract: A method of integrating benzocyclobutene (BCB) layers with a substrate is provided along with a corresponding device. A method includes forming a first BCB layer on the substrate and depositing a first metal layer on the first BCB layer and within vias defined by the first metal layer. The method also forms a second BCB layer on the first metal layer and deposits a second metal layer on the second BCB layer and within vias defined by the second metal layer. The second metal layer extends through the vias defined by the second metal layer to establish an operable connection with the first metal layer. The first and second metal layers are independent of an electrical connection to any circuit element carried by the substrate, but the first and second metal layers secure the second BCB layer to the underlying structure and reduce the likelihood of delamination.
    Type: Application
    Filed: December 2, 2011
    Publication date: June 6, 2013
    Applicant: THE BOEING COMPANY
    Inventors: Hasan Sharifi, Alexandros D. Margomenos, Ara K. Kurdoghlian, Miroslav Micovic, Keisuke Shinohara, Colleen M. Butler
  • Publication number: 20090102061
    Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SAWLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.
    Type: Application
    Filed: November 26, 2008
    Publication date: April 23, 2009
    Inventors: Hasan Sharifi, Saeed Mohammadi, Linda P.B. Katehi
  • Patent number: 7473579
    Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.
    Type: Grant
    Filed: January 27, 2006
    Date of Patent: January 6, 2009
    Assignee: Purdue Research Foundation
    Inventors: Hasan Sharifi, Saeed Mohammadi, Linda P. B. Katehi
  • Publication number: 20070278631
    Abstract: A polymer-based, self-aligned wafer-level heterogeneous integration system, SA WLIT, for integrating semiconductor integrated circuit (IC) chips to a substrate is presented. The system includes a method including preparing a substrate, flipping the substrate onto a polymer-based flat surface and securing the substrate to the flat surface, mounting semiconductor chips into the prepared substrate, integrating the chips to the substrate with another polymer-based material, and removing the resulting multi-chip module from the flat surface. The chips may then be connected with each other and regions off the multi-chip module with metal interconnect processing technology. A multi-chip module prepared by the polymer-based, self-aligned heterogeneous integration system including semiconductor chips mounted in a prepared substrate. The chips may be connected to the substrate by a polymer-based integrating material.
    Type: Application
    Filed: January 27, 2006
    Publication date: December 6, 2007
    Inventors: Hasan Sharifi, Saeed Mohammadi, Linda Katehi