Patents by Inventor Hau-Tai Shieh

Hau-Tai Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096400
    Abstract: A memory device includes a memory bank with a memory cell connected to a local bit line and a word line. A first local data latch is connected to the local bit line and has an enable terminal configured to receive a first local clock signal. A word line latch is configured to latch a word line select signal, and has an enable terminal configured to receive a second local clock signal. A first global data latch is connected to the first local data latch by a global bit line, and the first global data latch has an enable terminal configured to receive a global clock signal. A global address latch is connected to the word line latch and has an enable terminal configured to receive the global clock signal. A bank select latch is configured to latch a bank select signal, and has an enable terminal configured to receive the second local clock signal.
    Type: Application
    Filed: January 23, 2023
    Publication date: March 21, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan CHEN, Hau-Tai SHIEH, Cheng Hung LEE
  • Patent number: 11929109
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Grant
    Filed: April 25, 2023
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Publication number: 20240071428
    Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.
    Type: Application
    Filed: November 8, 2023
    Publication date: February 29, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Hsin YU, Hung-Jen LIAO, Cheng-Hung LEE, Hau-Tai SHIEH
  • Patent number: 11915743
    Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: February 27, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
  • Patent number: 11869623
    Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: January 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Hsin Yu, Hung-Jen Liao, Cheng-Hung Lee, Hau-Tai Shieh
  • Patent number: 11854970
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: December 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Publication number: 20230410854
    Abstract: A memory circuit includes a first and a second bit line coupled to a set of memory cells, a local input output circuit including a first and a second data line, a first control circuit configured to generate a first sense amplifier signal and a second sense amplifier signal, a second control circuit configured to generate a first control signal in response to at least a second control signal or a third control signal, a switching circuit configured to transfer a first and second input signal to the corresponding first and second data line during a write operation, and to electrically isolate the first and second data line from the first and second input signal during a read operation, and a first latch configured as a sense amplifier, during the read operation, and configured as a write-in latch, during the write operation.
    Type: Application
    Filed: January 20, 2023
    Publication date: December 21, 2023
    Inventors: Hua-Hsin YU, Hau-Tai SHIEH, Cheng Hung LEE, Hung-Jen LIAO
  • Publication number: 20230395122
    Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
    Type: Application
    Filed: August 4, 2023
    Publication date: December 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20230386567
    Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.
    Type: Application
    Filed: August 8, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao
  • Publication number: 20230378063
    Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 23, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Cheng-Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Kao-Cheng Lin, Wei-Min Chan
  • Publication number: 20230368826
    Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first P-type transistor coupled to the NAND logic gate, and configured to receive a first clock signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Application
    Filed: July 25, 2023
    Publication date: November 16, 2023
    Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
  • Patent number: 11817144
    Abstract: A memory device and a method of operating the same are disclosed. In one aspect, the memory device includes a plurality of memory arrays and a controller including a plurality of buffers including a first buffer connected to a first memory array and a second buffer connected to a second memory array. The first and second memory arrays are disposed on opposing sides of the controller. The memory device can include a first wire extending in a first direction and connected to the first buffer, a second wire extending in the first direction and connected to the second buffer, and a third wire connected to the first and second wires and extending in a second direction that is substantially perpendicular to the first direction. The third wire can be electrically connected to the controller, and respective lengths of the first wire and the second wire are substantially the same.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 14, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Hau-Tai Shieh, Cheng Hung Lee, Hung-Jen Liao
  • Patent number: 11763873
    Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: September 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Ju Yeh, Hau-Tai Shieh, Yi-Tzu Chen
  • Publication number: 20230282274
    Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a bit line connected to a plurality of memory cells of a memory array, the bit line having a first length. The memory device includes a first programmable bit line having a second length determined based on a size of the memory array, and a charge sharing circuit connected to the bit line and the first programmable bit line. The charge sharing circuit is configured to transfer a charge from the bit line to the first programmable bit line. The memory device includes a discharge circuit connected to the first programmable bit line, the discharge circuit configured to discharge a stored charge in the first programmable bit line.
    Type: Application
    Filed: March 2, 2022
    Publication date: September 7, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Yuan Chen, Che-An Lee, Hau-Tai Shieh, Cheng Hung Lee
  • Publication number: 20230267989
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Publication number: 20230245677
    Abstract: A method of designing a circuit is provided. The method includes: providing a circuit; selecting a first NMOS fin field-effect transistor (FinFET) in the circuit; and replacing the first NMOS FinFET having a first fin number with a second NMOS FinFET having a second fin number and a third NMOS FinFET having a third fin number, wherein the sum of the second fin number and the third fin number is equal to the first fin number.
    Type: Application
    Filed: January 30, 2023
    Publication date: August 3, 2023
    Inventors: Yi-Tzu Chen, Hau-Tai Shieh, Che-Ju Yeh
  • Patent number: 11715505
    Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: August 1, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
  • Patent number: 11682453
    Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. A control circuit includes a first transistor, an inverter coupled to the first transistor, and a second transistor comprising a gate, a first source/drain terminal and a second source/drain terminal. The second transistor is coupled to the inverter. The first source/drain terminal of the second transistor is coupled in series to the first transistor. The second source/drain terminal is coupled to a decoder driver circuit. The second transistor is configured to charge a load of a common decoder line so as to reduce an effective load of the decoder driver circuit.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: June 20, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
  • Patent number: 11670362
    Abstract: Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao
  • Publication number: 20230064056
    Abstract: A device is disclosed and includes an input stage circuit, a switching circuit, and a first latch circuit. The input stage circuit generates a first input signal having a first voltage and a second input signal based on a third input signal. The switching circuit operates in response to a first control signal, and adjusts a voltage level of a first data line according to the first input signal and a voltage level of a second data line according to the second input signal. The first latch circuit is coupled to the switching circuit by the first data line and the second data line. The first latch circuit latches a data in response to the first control signal and a second control signal, and adjusts the voltage level of the first data line based on a second voltage different from the first voltage.
    Type: Application
    Filed: August 30, 2021
    Publication date: March 2, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hua-Hsin YU, Hung-Jen LIAO, Cheng-Hung LEE, Hau-Tai SHIEH