Patents by Inventor Hau-Tai Shieh
Hau-Tai Shieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10651832Abstract: A level shifter is configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain. An input terminal is configured to receive an input signal in a first voltage domain. A first sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain, and a second sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain. An enable circuit is configured to equalize a voltage level of first and second output signals at respective first and second output terminals in response to an enable signal. The first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal.Type: GrantFiled: April 19, 2019Date of Patent: May 12, 2020Assignee: Taiwan Semiconductor Manufacturing Company, LTD.Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
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Publication number: 20200111526Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
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Patent number: 10614878Abstract: A module includes a high speed voltage node, a pre-charging circuit, and a cross coupled circuit. The pre-charging circuit includes a pre-charger configured to pre-charge complementary first and second lines of a memory device to a level of a source voltage. The cross coupled circuit is configured to pull one of the first and second lines to a level of a high speed voltage at the high speed voltage node higher than the level of the source voltage. As such, a memory cell of the memory device can be read at a high speed.Type: GrantFiled: September 23, 2016Date of Patent: April 7, 2020Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Hua-Hsin Yu, Hau-Tai Shieh
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Publication number: 20200052678Abstract: A level shifter is configured to receive an input signal in a first voltage domain and output an output signal in a second voltage domain. An input terminal is configured to receive an input signal in a first voltage domain. A first sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain, and a second sensing circuit is configured to shift the input signal from the first voltage domain to the second voltage domain. An enable circuit is configured to equalize a voltage level of first and second output signals at respective first and second output terminals in response to an enable signal. The first and second sensing circuits are configured output complementary output signals in the second voltage domain at the first and second output terminals in response to the enable signal and the input signal.Type: ApplicationFiled: April 19, 2019Publication date: February 13, 2020Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
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Publication number: 20200020386Abstract: A latch formed from a memory cell includes a clock input terminal configured to receive a clock signal, complementary first and second data terminals, and a latch circuit. The latch circuit has first and second inverters. The first inverter has an input terminal coupled to the first data terminal, and the second inverter has an input terminal coupled to the second data terminal. A first pass gate transistor is coupled between an output terminal of the second inverter and the first data terminal. A second pass gate transistor is coupled between an output terminal of the first inverter and the second data terminal. The first and second pass gate transistors each have a gate terminal coupled to the clock input terminal. The input terminal of the first inverter is not directly connected to the output terminal of the second inverter, and the input terminal of the second inverter is not directly connected to the output terminal of the first inverter.Type: ApplicationFiled: July 10, 2019Publication date: January 16, 2020Inventors: Hua-Hsin Yu, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh
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Publication number: 20200020413Abstract: Different embodiments of local redundancy decoder circuits that can be used in a memory device are disclosed. The different types of local redundancy decoder circuits are operably connected to the columns of memory cells in a memory array.Type: ApplicationFiled: July 11, 2019Publication date: January 16, 2020Inventors: Chien-Yu Huang, Chia-En Huang, Cheng Hung Lee, Hau-Tai Shieh
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Patent number: 10510401Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.Type: GrantFiled: May 16, 2018Date of Patent: December 17, 2019Assignee: Taiwan Semicondutor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
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Patent number: 10354719Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: GrantFiled: December 20, 2018Date of Patent: July 16, 2019Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Publication number: 20190122725Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Patent number: 10163489Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: GrantFiled: January 9, 2018Date of Patent: December 25, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Publication number: 20180342288Abstract: Devices and methods are provided for word line pulse width control for a static random access memory (SRAM) devices. An inverter within a pre-decoder circuit receives a first input of a clocked address. The inverter determines an output based on the clocked address. An electrical load of a decoder driver circuit of the SRAM device is modified based on the output. Current to a transistor coupled at a common node is provided. The transistor is configured to electrically couple a plurality of transistors of the decoder driver circuit within the SRAM device.Type: ApplicationFiled: May 3, 2018Publication date: November 29, 2018Inventors: Anjana Singh, Cheng Hung Lee, Hau-Tai Shieh, Yi-Tzu Chen
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Publication number: 20180336944Abstract: A semiconductor memory device comprising a plurality of memory cells configured to store digital data and an input multiplexer configured to enable the selection of a particular memory cell from the plurality of memory cells. The semiconductor memory device further comprises a read/write driver circuit configured to read data from the selected memory cell and write data to the selected memory cell, and a write logic block configured to provide logical control to the read/write driver circuit for writing data to the selected of memory cell. The read/write driver circuit may be coupled to the read/write input multiplexer by a data line and an inverted data line and the read and the write operations to the selected memory cell occur over the same data line and inverted data line.Type: ApplicationFiled: May 16, 2018Publication date: November 22, 2018Inventors: Chien-Yuan Chen, Che-Ju Yeh, Hau-Tai Shieh, Cheng-Hung Lee, Hung-Jen Liao, Sahil Preet Singh, Manish Arora, Hemant Patel, Li-Wen Wang
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Publication number: 20180226412Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: ApplicationFiled: April 6, 2018Publication date: August 9, 2018Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Patent number: 9979399Abstract: A circuit is disclosed. The circuit includes eight MOD transistors and a capacitor, the first MOS transistor having a source coupled to a first predetermined supply voltage (VDDM), a second MOS transistor having a source coupled to a first predetermined supply voltage VDDM, a third MOS transistor having a source coupled to a drain of the first MOS transistor, a fourth MOS transistor having a source coupled to a drain of the second MOS transistor, a fifth MOS transistor having a source coupled to a drain of the third MOS transistor and a gate of the second MOS transistor, and a gate coupled to a gate of the third MOS transistor and an input node, and a drain coupled to ground, a sixth MOS transistor having a source coupled to a drain of the fourth MOS transistor and a gate of the first MOS transistor and an output node.Type: GrantFiled: March 18, 2016Date of Patent: May 22, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Yuan Chen, Cheng Hung Lee, Hung-Jen Liao, Hau-Tai Shieh, Che-Ju Yeh
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Publication number: 20180130519Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: ApplicationFiled: January 9, 2018Publication date: May 10, 2018Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh
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Patent number: 9941287Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. An example SRAM device includes a first array of SRAM cells, a second array of SRAM cells, a processing component, and one or more inter-layer connection structures. The first array of SRAM cells are formed in a first device layer of a multi-layer semiconductor device structure. The second array of SRAM cells are formed in a second device layer of the multi-layer semiconductor device structure, the second device layer being formed on the first device layer. The processing component is configured to process one or more input signals and generate one or more access signals. One or more inter-layer connection structures are configured to transmit the one or more access signals to activate the first device layer or the second device layer for allowing access to a target SRAM cell.Type: GrantFiled: January 20, 2017Date of Patent: April 10, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yu Huang, Chien-Yuan Chen, Hau-Tai Shieh
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Publication number: 20180090188Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Yi-Tzu Chen, Anjana Singh, Che-Ju Yeh, Hau-Tai Shieh
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Publication number: 20180090189Abstract: A module includes a high speed voltage node, a pre-charging circuit, and a cross coupled circuit. The pre-charging circuit includes a pre-charger configured to pre-charge complementary first and second lines of a memory device to a level of a source voltage. The cross coupled circuit is configured to pull one of the first and second lines to a level of a high speed voltage at the high speed voltage node higher than the level of the source voltage. As such, a memory cell of the memory device can be read at a high speed.Type: ApplicationFiled: September 23, 2016Publication date: March 29, 2018Inventors: Hua-Hsin Yu, Hau-Tai Shieh
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Patent number: 9928888Abstract: A memory device includes a memory cell, a local bit line, a data line, first and second pass gate circuits, and a sense amplifier. The local bit line is coupled to the memory cell. The first pass gate circuit is coupled to the local bit line and the data line and is configured to couple the local bit line to the data line. The second pass gate circuit is coupled to the data line and the global bit line and is configured to couple the data line to the global bit line. The sense amplifier is coupled to the data line.Type: GrantFiled: September 23, 2016Date of Patent: March 27, 2018Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Yi-Tzu Chen, Anjana Singh, Che-Ju Yeh, Hau-Tai Shieh
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Patent number: 9875789Abstract: Systems are provided for a three dimension static random access memory (SRAM) structure. The SRAM structure comprises a plurality of memory array layers, layer decoder circuitry on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs extending vertically from a memory cell in a first memory array layer to a memory cell in a second memory array layer. The layer decoder circuitry on each memory array layer is configured to decode a portion of an SRAM address to determine if the SRAM address corresponds to memory cells on its memory array layer. The word line driver circuit disposed on each memory array layer is configured to operate cooperatively with a partial SRAM address decoder to select and drive one of the plurality of word lines disposed on its memory array layer, wherein a selected word line is connected to a predetermined number of memory cells in a specific memory array layer.Type: GrantFiled: November 22, 2013Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Yuan Chen, Chien-Yu Huang, Hau-Tai Shieh