Abstract: A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter. The first inverter has a first pull-up transistor with a first pull-up terminal. The second inverter has a second pull-up transistor with a second pull-up terminal. The output of the first inverter is coupled to the input of the second inverter at a first sense amp node. The output of the second inverter is coupled to the input of the first inverter at a second sense amp node. The data line charging circuit has a first node connected to a data line and the first pull-up terminal. The data line charging circuit also has a second node connected to a complementary data line and the second pull-up terminal. The first and second pull-up transistors are coupled to different voltage levels when a sense amplifier enable signal is activated.

Abstract: An apparatus comprises a first signal input, a first transistor, a first line, a first circuit coupled to the first transistor through the first line, a second line coupled to the first line between the first transistor and the first circuit, a second transistor coupled to the first transistor through the second line, a second circuit coupled to the second transistor, the first circuit being a replica of the second circuit, a second signal input, and a third transistor coupled to the second signal input and the second circuit. The apparatus maintains a virtual voltage of the second circuit above a predetermined threshold by a voltage associated with the second line. The voltage associated with the second line is based on a difference between a first current associated with a portion of the first line and a second current associated with another portion of the first line.

Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.

Abstract: Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer. Each memory array layer comprises a plurality of memory cells and a word line disposed thereon. Each word line is connected to the plurality of memory cells disposed on its memory array layer. The number of memory cells in a layer corresponds to a predetermined memory page size. Each layer decoder circuit is configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer. Each word line driver circuit is configured to drive the word line disposed on its memory array layer.

Abstract: A circuit includes stacked memory arrays and a control circuit. The stacked memory arrays includes a first layer and a second layer. The control circuit is configured to receive a first address in the first layer; cause the second layer to be enabled for accessing; and provide a second row address for accessing the second layer.

Abstract: A sense amplifier circuit comprising a pair of cross-coupled inverters and a data line charging circuit is disclosed. The cross-coupled inverters comprise a first inverter and a second inverter. The first inverter has a first pull-up transistor with a first pull-up terminal. The second inverter has a second pull-up transistor with a second pull-up terminal. The output of the first inverter is coupled to the input of the second inverter at a first sense amp node. The output of the second inverter is coupled to the input of the first inverter at a second sense amp node. The data line charging circuit has a first node connected to a data line and the first pull-up terminal. The data line charging circuit also has a second node connected to a complementary data line and the second pull-up terminal. The first and second pull-up transistors are coupled to different voltage levels when a sense amplifier enable signal is activated.

Abstract: Disclosed is a novel static random access memory (SRAM) device. The SRAM device comprises a plurality of memory array layers vertically disposed one above another, a layer decoder circuit disposed on each memory array layer, a word line driver circuit disposed on each memory array layer, and a plurality of complementary bit line pairs wherein each complementary bit line pair extends vertically to couple a memory cell in each memory array layer. Each memory array layer comprises a plurality of memory cells and a word line disposed thereon. Each word line is connected to the plurality of memory cells disposed on its memory array layer. The number of memory cells in a layer corresponds to a predetermined memory page size. Each layer decoder circuit is configured to decode a portion of an SRAM address to select its memory array layer if the SRAM address corresponds to memory cells on its memory array layer. Each word line driver circuit is configured to drive the word line disposed on its memory array layer.

Abstract: Systems and methods are provided for fabricating a static random access memory (SRAM) cell in a multi-layer semiconductor device structure. The SRAM cell includes two pull-up transistors, two pull-down transistors, a plurality of operation-assistance transistors, and two pass-gate transistors. The first pull-up transistor and the second pull-up transistor are formed in a first device layer of the multi-layer semiconductor device structure. The first pull-down transistor and the second pull-down transistor are formed in a second device layer of the multi-layer semiconductor device structure. The plurality of operation-assistance transistors are formed in the first device layer and configured to provide local supply voltages to the first pull-up transistor and the second pull-up transistor respectively. The first pass-gate transistor and the second pass-gate transistor are formed in the second device layer and configured to provide access to the data bit.

Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.

Abstract: An integrated circuit structure includes one or more external contact pads with decoupling capacitors, such as metal-insulator-metal (MIM) capacitors, formed directly thereunder. In an embodiment, the decoupling capacitors are formed below the first metallization layer, and in another embodiment, the decoupling capacitors are formed in the uppermost inter-metal dielectric layer. A bottom plate of the decoupling capacitors is electrically coupled to one of Vdd and Vss, and the top plate of the decoupling capacitors is electrically coupled to the other. The decoupling capacitors may include an array of decoupling capacitors formed under the external contact pads and may include one or more dummy decoupling capacitors. The one or more dummy decoupling capacitors are MIM capacitors in which at least one of the top plate and the bottom plate is not electrically coupled to an external contact pad.

Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.

Abstract: Some embodiments relate to a sense amplifier output buffer configured to buffer an output of a sense amplifier. The sense amplifier output buffer includes a first pull-up element having a source coupled to a first DC supply terminal and having a drain coupled to an output terminal of the sense amplifier output buffer. A first pull-down element is in series with the first pull-up element and has a source coupled to a second DC supply terminal and has a drain coupled to the output terminal. A miller capacitance decoupling circuit is coupled between the drain of the first pull-up element and the drain of the first pull-down element. The miller capacitance decoupling circuit is configured to decouple miller capacitance associated with the drains of the pull-up and pull-down elements from the output terminal. Other embodiments are also disclosed.

Abstract: Among other things, techniques for facilitating a write operation to a bit cell are provided. A pulse generator initializes lowering of an internal voltage level associated with a bit cell that is to be written to by a write operation. In this way, the bit cell is placed into a writeable voltage state, such that a potential of the bit cell can be overcome by the write operation. A voltage detector sends a reset signal to the pulse generator based upon the pulse generator lowering the internal voltage level past a reset trigger level. Responsive to receiving the reset signal, the pulse generator initializes charging of the internal voltage level to an original voltage level. In this way, the lowering of the internal voltage level is controlled so that one or more other bit cells are not affected (e.g., suffer data retention failure) by the relatively lower internal voltage level.

Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: In at least one embodiment, a multiplexer has a plurality of sub-circuits, and each of the plurality of sub-circuits has a first transistor, a second transistor, and a third transistor. Drains of the first transistors are coupled with a first terminal of a fourth transistor, and drains of the second transistors are coupled with a second terminal of the fourth transistor. In at least one embodiment, a method of outputting data using the multiplexer includes turning on the second transistor of a selected one of the plurality of sub-circuits responsive to a clock signal and address information. The second transistor of a non-selected one of the plurality of sub-circuits is turned off. The fourth transistor is turned on responsive to the clock signal.

Abstract: A multiplexing circuit includes a plurality of first circuits and a second circuit coupled to outputs of the plurality of first circuits. A first circuit of the plurality of first circuits is configured to receive a first data line as a first input and a clock signal as a second input, and provide an output signal to a first circuit output. After the first circuit is selected for use, the clock signal, a first sub-circuit of the first circuit coupled to the second circuit, and the second circuit are configured to provide a first output logic level to the output signal based on a first data logic level of the first data line; and a second sub-circuit of the first circuit coupled to the first circuit output is configured to provide a second output logic level to the output signal based on a second data logic level of the first data line.

Abstract: Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.