Abstract: A semiconductor photonics device includes a plurality of grating couplers, each configured to couple a particular wavelength (or wavelength range) of an optical signal to a waveguide of the semiconductor photonics device. In some implementations, various implementations of optical signal splitters or filters described herein enable respective wavelengths (or respective wavelength ranges) to be passed to each of the grating couplers (while filtering out other wavelengths or other wavelength ranges), thereby enabling the grating couplers to each handle a respective wavelength (or respective wavelength range). This enables multiple wavelengths (or multiple wavelength ranges) to be distributed across multiple grating couplers, which may increase the bandwidth of the semiconductor photonics device relative to a semiconductor photonics device that includes only a single grating coupler.

Abstract: A photodetector may include an absorption region that is formed to have an increasing depth (or thickness) in a direction that is approximately parallel to the direction of incident light that is to be projected onto the absorption region. The increasing depth of the absorption region in the direction that is approximately parallel with the direction of incident light enables the incident light to be more uniformly distributed along the length of the absorption region in the direction that is approximately parallel with the direction of incident light. This reduces the likelihood that a particular area of the absorption region reaches optical saturation, which may enable the photodetector to operate a sustained high photodetector sensitivity and/or a sustained high light detection performance, among other examples.

Abstract: A semiconductor structure includes a waveguide and an optical attenuator. The waveguide is disposed over an insulating layer and configured to guide light. The optical attenuator is connected to the waveguide. The optical attenuator has a first surface and a second surface opposite the first surface, and a cross-sectional width of the optical attenuator decreases from the first surface to the second surface.

Abstract: A photonic device includes a substrate, a P-type doped component disposed over the substrate, an N-type doped component disposed over the substrate, an optical absorption layer disposed over the substrate, and a charging layer disposed over the substrate. The optical absorption layer is disposed between the P-type doped component and the N-type doped component. The optical absorption layer and the substrate have different material compositions. A charging layer is disposed between the P-type doped component and the N-type doped component. The charging layer has a first side surface that is substantially linear. The first side surface is in direct contact with the optical absorption layer.

Abstract: An edge coupler includes a substrate, a first cladding layer over the substrate, a core layer over the first cladding layer, and an ARC layer. The substrate has a first sidewall, the first cladding layer has a second sidewall aligned with the first sidewall, and the core layer has a third sidewall aligned with the second sidewall. The ARC layer lines the first sidewall, the second sidewall and the third sidewall. The ARC layer physically contacts and covers a surface of the substrate. A first height of the ARC layer varies along the surface of the substrate.

Abstract: A method of forming a grating coupler includes: providing an initial design layout of the grating coupler, wherein the initial design layout includes: a taper section, comprising a pair of tapers; and a grating section coupled to the taper section, the grating section having an array of gratings, wherein the gratings includes gradually changing shapes, from a top-view perspective, from a first non-convex octagonal shape of a central grating, at a center of the grating section, of one of a second non-convex octagonal shape, a convex octagonal shape, and a quadrilateral shape, to an edge grating near an edge of the grating section. The method further includes: converting the initial design layout into a revised design layout through an optical proximity correction operation; and manufacturing the grating coupler using the revised design layout.

Abstract: An edge coupler, a waveguide structure and a method for forming a waveguide structure are provided. The edge coupler includes a substrate, a first cladding layer, a core layer and a first anti-reflection coating layer. The first cladding layer has a second sidewall aligned with a first sidewall of the substrate. The core layer has a third sidewall aligned with the second sidewall. The anti-reflection coating layer lines the first sidewall, the second sidewall and the third sidewall. A thickness of the anti-reflection coating layer varies along the first sidewall, the second sidewall and the third sidewall.

Abstract: In some embodiments, the present disclosure relates to a device having a first waveguide and a second waveguide arranged over a substrate. The first waveguide has a first input terminal and a first output terminal, wherein the first input terminal is configured to receive light. The second waveguide is arranged laterally beside the first waveguide and has a second input terminal and a second output terminal. The second input terminal of the second waveguide is configured to receive light. The first waveguide further includes a first portion that has a different structure than surrounding portions of the first waveguide. The second waveguide further includes a second portion that has a different structure than surrounding portions of the second waveguide. The first waveguide is spaced apart at a maximum distance from the second waveguide at the first portion and the second portion.

Abstract: An edge coupler has a wide end, a narrow end, and a tapering thickness. The narrow end is coupled to a waveguide in a photonic integrated circuit (PIC). The wide end is coupled to an optical transmitter or receiver. The edge coupler thickens by tapering downward into the buried oxide layer of a BOX substrate. An upper surface of the edge coupler may be planar. A pedestal may be formed in the oxide layer so that a laser diode mounted on the pedestal will be vertically aligned to the edge coupler. Alternatively, the pedestal may be formed in a substrate under the oxide layer so that the core of an optical fiber mounted on the pedestal will be vertically aligned to the edge coupler. The pedestal may be in a cavity that facilitates horizontal alignment between the laser diode, optical fiber, or other such device and the edge coupler.

Abstract: In some embodiments, the present disclosure relates to a device having a first waveguide and a second waveguide arranged over a substrate. The first waveguide has a first input terminal and a first output terminal, wherein the first input terminal is configured to receive light. The second waveguide is arranged laterally beside the first waveguide and has a second input terminal and a second output terminal. The second input terminal of the second waveguide is configured to receive light. The first waveguide further includes a first portion that has a different structure than surrounding portions of the first waveguide. The second waveguide further includes a second portion that has a different structure than surrounding portions of the second waveguide. The first waveguide is spaced apart at a maximum distance from the second waveguide at the first portion and the second portion.

Abstract: Some implementations described herein include a photonics integrated circuit device including a photonics structure. The photonics structure includes a waveguide structure and an optical attenuator structure. In some implementation, the optical attenuator structure is formed on an end region of the waveguide structure and includes a metal material or a doped material. In some implementations, the optical attenuator structure includes a gaussian doping profile within a portion of the waveguide structure. The optical attenuator structure may absorb electromagnetic waves at the end of the waveguide structure with an efficiency that is improved relative to a spiral optical attenuator structure or metal cap optical attenuator structure.

Abstract: A coupling system includes an optical fiber configured to carry an optical signal. The coupling system further includes a grating on a first side of a semiconductor layer, wherein the grating is configured to receive the optical signal. The coupling system further includes an interconnect structure over the grating on the first side of the semiconductor layer, wherein the interconnect structure defines a cavity aligned with the grating. The coupling system further includes a first polysilicon layer on a second side of the semiconductor layer, wherein the second side of the semiconductor layer is opposite to the first side of the semiconductor layer.

Abstract: Some embodiments relate to an integrated chip (IC) including a handle substrate; a semiconductor layer comprising a grating coupler region and an edge coupler region; an insulative layer between the handle substrate and the semiconductor layer; a grating coupler in the grating coupler region comprising a plurality of trenches arranged in the semiconductor layer; and an edge coupler in the edge coupler region of the semiconductor layer including: a base structure having an end proximate to an edge of the insulative layer, and tapered sidewalls extending laterally from the end; and an upper structure extending over the base structure, the upper structure having an end proximate to the edge of the insulative layer, and tapered sidewalls extending laterally from the end between the tapered sidewalls of the base structure; where the handle substrate continuously extends from directly beneath the plurality of trenches to directly beneath the upper structure.

Abstract: Various embodiments of the present disclosure are directed towards a photonic device including a temperature adjustment element. A first waveguide overlies an insulating layer. A second waveguide overlies the insulating layer. The temperature adjustment element includes a heater structure aligned with a segment of the first waveguide and a cooler structure aligned with a segment of the second waveguide. The heater structure is configured to increase a temperature of the segment of the first waveguide to a first temperature. The cooler structure is configured to reduce a temperature of the segment of the second waveguide to a second temperature less than the first temperature.

Abstract: Depositing an oxide material on sidewalls of trenches between etching cycles allows narrower trenches to be etched to increased depths without causing over-etching of wider trenches. As a result, efficiency of a device including the trenches (e.g., a silicon photonics (SiPh) device or a pixel device, among other examples) is increased. For example, because light leakage and light scattering is reduced in an SiPh device, power is conserved at a transmission device that can decrease transmit power on account of the increased efficiency.

Abstract: An integrated chip including a base dielectric layer and a multi-tiered semiconductor waveguide layer over the base dielectric layer. The multi-tiered semiconductor waveguide layer has a first waveguide tier having a first width at a first height over the base dielectric layer. The multi-tiered semiconductor waveguide layer has a second waveguide tier having a second width, greater than the first width, at a second height, less than the first height, over the base dielectric layer. A cladding layer is over the multi-tiered semiconductor waveguide layer. A multi-tiered conductive heater layer is over the cladding layer. The multi-tiered conductive heater layer has a first heater tier over the first waveguide tier. The multi-tiered conductive heater layer has a pair of second heater tiers at the first height, over the second waveguide tier, and on opposite sides of the first waveguide tier.

Abstract: A method for forming an optical waveguide structure includes following operations. A substrate is received. A semiconductor layer is formed on the substrate. The semiconductor layer is patterned to form at least a waveguide in the substrate and at least a trench in the semiconductor layer. A first gap-filling operation is performed to form a first dielectric portion in the trench. A second gap-filling operation is performed to form a second dielectric portion over the first dielectric portion. An air seam is sealed within the second dielectric portion. A third gap-filling operation is performed to form a third dielectric portion over the second dielectric portion.

Abstract: Some implementations described herein include a photonics integrated circuit device including a photonics structure. The photonics structure includes a waveguide structure and an optical attenuator structure. In some implementation, the optical attenuator structure is formed on an end region of the waveguide structure and includes a metal material or a doped material. In some implementations, the optical attenuator structure includes a gaussian doping profile within a portion of the waveguide structure. The optical attenuator structure may absorb electromagnetic waves at the end of the waveguide structure with an efficiency that is improved relative to a spiral optical attenuator structure or metal cap optical attenuator structure.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor package comprising optically coupled integrated circuit (IC) chips. A first IC chip and a second IC chip overlie a substrate at a center of the substrate. A photonic chip overlies the first and second IC chips and is electrically coupled to the second IC chip. A laser device chip overlies the substrate, adjacent to the photonic chip and the second IC chip, at a periphery of the substrate. The photonic chip is configured to modulate a laser beam from the laser device chip in accordance with an electrical signal from the second IC chip and to provide the modulated laser beam to the first IC chip. This facilitates optical communication between the first IC chip to the second IC chip. Various embodiments of the present disclosure are further directed towards simultaneously aligning and bonding constituents of the semiconductor package.

Abstract: A method of making a chip includes depositing a first polysilicon layer on a top surface and a bottom surface of a substrate. The method further includes patterning the first polysilicon layer to define a recess, wherein the first polysilicon layer is completed removed from the recess. The method further includes implanting dopants into the substrate to define an implant region. The method further includes depositing a contact etch stop layer (CESL) in the recess, wherein the CESL covers the implant region. The method further includes patterning the CESL to define a CESL block. The method further includes forming a waveguide and a grating in the substrate. The method further includes forming an interconnect structure over the waveguide, the grating and the CESL block. The method further includes etching the interconnect structure to define a cavity aligned with the grating.