Patents by Inventor Hau-yan Lu
Hau-yan Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180308847Abstract: A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.Type: ApplicationFiled: April 20, 2017Publication date: October 25, 2018Inventors: Hau-Yan LU, Shih-Hsien CHEN, Chun-Yao KO, Felix Ying-Kit TSUI
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Patent number: 10043919Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.Type: GrantFiled: August 19, 2016Date of Patent: August 7, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Patent number: 9711516Abstract: A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.Type: GrantFiled: October 30, 2015Date of Patent: July 18, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shih-Hsien Chen, Hau-Yan Lu, Liang-Tai Kuo, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20170194338Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.Type: ApplicationFiled: March 22, 2017Publication date: July 6, 2017Inventors: Shih-Hsien CHEN, Liang-Tai KUO, Hau-Yan LU, Chun-Yao KO
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Publication number: 20170194342Abstract: A semiconductor device is provided. The semiconductor device comprises a first active region, a second active region and a third active region, a first poly region, a second poly region, a third poly region, a first doped region and a second doped region. The first active region, the second active region and the third active region are separated and parallel with each other. The first poly region is arranged over the first and second active regions. The second poly region is arranged over the first and second active regions. The third poly region is arranged over the second and third active regions. The first doped region is in the second active region and between the first poly region and the second poly region. The second doped region is in the second active region and between the second poly region and the third poly region.Type: ApplicationFiled: January 4, 2016Publication date: July 6, 2017Inventors: HAU-YAN LU, SHIH-HSIEN CHEN, CHUN-YAO KO, FELIX YING-KIT TSUI
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Publication number: 20170125425Abstract: A non-volatile memory structure includes a semiconductor substrate and a first layer of a first dopant type in the semiconductor substrate. The non-volatile memory structure further includes a first well region of a second dopant type over the first layer, a second well region of the second dopant type over the first layer and spaced apart from the first well region, and a third well region of the first dopant type disposed between the first well region and the second well region and extending downward to the first layer.Type: ApplicationFiled: October 30, 2015Publication date: May 4, 2017Inventors: SHIH-HSIEN CHEN, HAU-YAN LU, LIANG-TAI KUO, CHUN-YAO KO, FELIX YING-KIT TSUI
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Patent number: 9620594Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.Type: GrantFiled: September 29, 2014Date of Patent: April 11, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Hsien Chen, Liang-Tai Kuo, Hau-Yan Lu, Chun-Yao Ko
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Patent number: 9537016Abstract: A memory device is disclosed. The memory device includes a substrate, including a substrate, including a source region and a drain region; and a gate stack, formed over a surface of the substrate, wherein the gate stack includes: a tunneling layer; a first layer; a second layer; a third layer; and a blocking layer; wherein each of the tunneling layer and the blocking layer has an oxygen proportion higher than the first, the second and the third layers; the first layer has a highest silicon proportion among the first, the second and the third layers; the second layer has a highest oxygen proportion among the first, the second and the third layers; and the first layer has a highest nitrogen proportion among the first, the second and the third layers. An associated gate stack and a manufacturing method are also disclosed.Type: GrantFiled: February 3, 2016Date of Patent: January 3, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hau-Yan Lu, Chun-Yao Ko, Chun-Heng Liao, Felix Ying-Kit Tsui
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Publication number: 20160359052Abstract: Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Patent number: 9431107Abstract: Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.Type: GrantFiled: December 14, 2012Date of Patent: August 30, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Patent number: 9384815Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.Type: GrantFiled: October 8, 2013Date of Patent: July 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hsien Chen, Hau-Yan Lu, Liang-Tai Kuo, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20160093628Abstract: A memory device includes at least one memory cell. The memory cell includes first and second transistors, and first and second capacitors. The first transistor is coupled to a source line. The second transistor is coupled to the first transistor and a bit line. The first capacitor is coupled to a word line and the second transistor. The second capacitor is coupled to the second transistor and an erase gate.Type: ApplicationFiled: September 29, 2014Publication date: March 31, 2016Inventors: Shih-Hsien CHEN, Liang-Tai KUO, Hau-Yan LU, Chun-Yao KO
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Patent number: 9257522Abstract: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.Type: GrantFiled: September 29, 2014Date of Patent: February 9, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20150098266Abstract: Memory cells and operation methods thereof are provided. A memory device includes a number of memory cells. Each of the memory cells includes a first transistor, a switch and a capacitor. The first transistor has a drain connected to a corresponding bit-line. The switch has a first terminal connected to a source of the first transistor and a second terminal coupled to a reference voltage. The capacitor has a first plate and a second plate, and the first plate of the capacitor is electrically connected to a gate of the first transistor. The second plate of the capacitor is connected to a corresponding word line. The switch is turned off when the memory cell is not selected to perform a write operation or a read operation.Type: ApplicationFiled: October 8, 2013Publication date: April 9, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hsien CHEN, Hau-Yan LU, Liang-Tai KUO, Chun-Yao KO, Felix Ying-Kit TSUI
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Publication number: 20150016180Abstract: Some embodiments relate to a memory cell to store one or more bits of data. The memory cell includes a capacitor including first and second capacitor plates which are separated from one another by a dielectric. The first capacitor plate corresponds to a doped region disposed in a semiconductor substrate, and the second capacitor plate is a polysilicon or metal layer arranged over the doped region. The memory cell also includes a transistor laterally spaced apart from the capacitor and including a gate electrode arranged between first and second source/drain regions. An interconnect structure is disposed over the semiconductor substrate and couples the gate electrode of the transistor to the second capacitor plate.Type: ApplicationFiled: September 29, 2014Publication date: January 15, 2015Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Patent number: 8848428Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.Type: GrantFiled: July 13, 2012Date of Patent: September 30, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui
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Publication number: 20140167127Abstract: Memory devices and methods of manufacture thereof are disclosed. In one embodiment, a memory device includes a transistor having a gate disposed over a workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The memory device includes an erase gate having a tip portion that extends towards the workpiece. The erase gate is coupled to the gate of the transistor.Type: ApplicationFiled: December 14, 2012Publication date: June 19, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Alexander Kalnitsky, Hsiao-Chin Tuan, Felix Ying-Kit Tsui, Hau-Yan Lu
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Patent number: 8724363Abstract: An anti-fuse memory with coupling channel is provided. The anti-fuse memory includes a substrate of a first conductive type, a doped region of a second conductive type, a coupling gate, a gate dielectric layer, an anti-fuse gate, and an anti-fuse layer. The substrate has an isolation structure. The doped region is disposed in the substrate. A channel region is defined between the doped region and the isolation structure. The coupling gate is disposed on the substrate between the doped region and the isolation structure. The coupling gate is adjacent to the doped region. The gate dielectric layer is disposed between the coupling gate and the substrate. The anti-fuse gate is disposed on the substrate between the coupling gate and the isolation structure. The anti-fuse gate and the coupling gate have a space therebetween. The anti-fuse layer is disposed between the anti-fuse gate and the substrate.Type: GrantFiled: March 6, 2012Date of Patent: May 13, 2014Assignee: eMemory Technology Inc.Inventors: Hau-Yan Lu, Hsin-Ming Chen, Ching-Sung Yang
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Patent number: 8638589Abstract: An operating method for a memory unit is provided, wherein the memory unit includes a well region, a select gate, a first gate, a second gate, an oxide nitride spacer, a first diffusion region, and a second diffusion region. The operating method for the memory unit comprises the following steps. During a programming operation, a breakdown voltage is coupled to the second diffusion region through a first channel region formed under the select gate. A programming voltage is sequentially or simultaneously applied to the first gate and the second gate to rupture a first oxide layer and a second oxide layer, wherein the first oxide layer is disposed between the first gate and the well region, and the second oxide layer is disposed between the second gate and the well region.Type: GrantFiled: February 6, 2012Date of Patent: January 28, 2014Assignee: eMemory Technology Inc.Inventors: Hau-Yan Lu, Hsin-Ming Chen, Ching-Sung Yang
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Publication number: 20140016399Abstract: One embodiment relates to a memory device including a plurality of memory units tiled together to form a memory array. A memory unit includes a plurality of memory cells, which include respective capacitors and respective transistors, disposed on a semiconductor substrate. The capacitors include respective lower plates disposed in a conductive region in the semiconductor substrate. A wordline extends over the conductive region, and a contact couples the wordline to the conductive region so as to couple the wordline to the lower plates of the respective capacitors. The respective transistors are arranged so successive gates of the transistors are arranged on alternating sides of the wordline.Type: ApplicationFiled: July 13, 2012Publication date: January 16, 2014Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hau-Yan Lu, Shih-Hsien Chen, Chun-Yao Ko, Felix Ying-Kit Tsui