Patents by Inventor Hayato Iwamoto

Hayato Iwamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7341827
    Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of anmonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthl ether. The separation-material composition for the photo-resist is mainly used for a medicinal liquid washing liquid/scientific liquid in order to remove the photo-resist residuals and the by-product polymer after an ashing process of a photo-resist mask.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: March 11, 2008
    Assignees: Sony Corporation, EKC Technology K.K.
    Inventors: Masafumi Muramatsu, Hayato Iwamoto, Kazumi Asada, Tomoko Suzuki, Toshitaka Hiraga, Tetsuo Aoyama
  • Publication number: 20070215971
    Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 20, 2007
    Applicant: Sony Corporation
    Inventors: Yuichi Yamamoto, Hayato Iwamoto
  • Patent number: 7252778
    Abstract: An etching method and etching device are provided, enabling uniform rendering of the thickness of a film for processing on a wafer regardless of the film thickness profile thereof, and thereby enabling global planarizing of the wafer surface. In an etching method, the film thickness profile of the film for processing formed on the wafer is ascertained in advance, and wet etching is performed by discharging an etchant liquid L1 at a thick portion of the film for processing; simultaneously with the discharge of the etchant liquid L1, a diluting liquid L2 for the etchant liquid L1 is discharged at a thin portion of the film for processing.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: August 7, 2007
    Assignee: Sony Corporation
    Inventors: Hayato Iwamoto, Kei Kinoshita, Hajime Ugajin
  • Publication number: 20070105242
    Abstract: There is provided a substrate treatment method for performing treatment by feeding a chemical liquid to a surface of a substrate, in which, before feeding the chemical liquid to a predetermined area of the substrate, a liquid substance having a resistivity lower than that of the chemical liquid is fed to the surface of the substrate so that the liquid substance wets at least the predetermined area, and then, the chemical liquid is fed to the predetermined area so that the treatment is performed on the substrate with the chemical liquid fed to the surface of the substrate.
    Type: Application
    Filed: October 4, 2006
    Publication date: May 10, 2007
    Applicant: Sony Corporation
    Inventors: Yoshimichi Shiki, Seiji Oda, Hayato Iwamoto, Yoshiya Hagimoto
  • Publication number: 20060249803
    Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.
    Type: Application
    Filed: May 26, 2006
    Publication date: November 9, 2006
    Inventors: Yuichi Yamamoto, Hayato Iwamoto
  • Publication number: 20060244078
    Abstract: An etching method and etching device are provided, enabling uniform rendering of the thickness of a film for processing on a wafer regardless of the film thickness profile thereof, and thereby enabling global planarizing of the wafer surface. In an etching method, the film thickness profile of the film for processing formed on the wafer is ascertained in advance, and wet etching is performed by discharging an etchant liquid L1 at a thick portion of the film for processing; simultaneously with the discharge of the etchant liquid L1, a diluting liquid L2 for the etchant liquid L1 is discharged at a thin portion of the film for processing.
    Type: Application
    Filed: July 13, 2006
    Publication date: November 2, 2006
    Inventors: Hayato Iwamoto, Kei Kinoshita, Hajime Ugajin
  • Patent number: 7101726
    Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.
    Type: Grant
    Filed: November 3, 2004
    Date of Patent: September 5, 2006
    Assignee: Sony Corporation
    Inventors: Yuichi Yamamoto, Hayato Iwamoto
  • Patent number: 7087563
    Abstract: A resist stripping composition capable of reliably stripping off resist residue or polymer residue and keeping damage to the interconnects to a minimum and a method of producing a semiconductor device using the same, where the resist stripping composition comprises a salt of hydrofluoric acid and a base not including a metal, an organic solvent, a sugar alcohol such as xylitol, and water and has a hydrogen ion concentration of at least 8.
    Type: Grant
    Filed: December 4, 2002
    Date of Patent: August 8, 2006
    Assignees: Sony Corporation, EKC Technology K.K.
    Inventors: Hayato Iwamoto, Ryuichi Kanamura, Ai Endou, Tomoko Suzuki, Toshitaka Hiraga
  • Publication number: 20050252526
    Abstract: A single wafer cleaning method and a cleaning apparatus thereof are provided in which the transition to rinse treatment is swiftly performed without being influenced by a chemical liquid component, and a polymer and a residue of chemical liquid are suppressed to reduce defects on a substrate. The single wafer cleaning method according to an embodiment of the present invention is a single wafer cleaning method of performing cleaning by a chemical liquid 8 and a rinse liquid 14 while rotating a substrate-to-be-cleaned 30, in which after chemical liquid treatment is performed by moving a chemical liquid nozzle 10 over the substrate-to-be-cleaned 30, rinse treatment is performed on the substrate-to-be-cleaned 30 by discharging the rinse liquid 14 from a rinse nozzle 16 disposed fixedly at a position not interfering with the movement of the chemical liquid nozzle 10.
    Type: Application
    Filed: April 28, 2005
    Publication date: November 17, 2005
    Applicant: Sony Corporation
    Inventors: Naoki Ogawa, Hayato Iwamoto, Kazumi Asada, Mari Yokota, Yasuhiro Hiei, Tsuyoshi Nishimatsu
  • Publication number: 20050104148
    Abstract: A solid state imaging device having a back-illuminated type structure in which a lens is formed on the back side of a silicon layer with a light-receiving sensor portion being formed thereon. Insulating layers are buried into the silicon layer around an image pickup region, with the insulating layer being buried around a contact layer that connects an electrode layer of a pad portion and an interconnection layer of the surface side. A method of manufacturing such a solid-state imaging device is also provided.
    Type: Application
    Filed: November 3, 2004
    Publication date: May 19, 2005
    Applicant: Sony Corporation
    Inventors: Yuichi Yamamoto, Hayato Iwamoto
  • Publication number: 20050000940
    Abstract: An etching method and etching device are provided, enabling uniform rendering of the thickness of a film for processing on a wafer regardless of the film thickness profile thereof, and thereby enabling global planarizing of the wafer surface. In an etching method, the film thickness profile of the film for processing formed on the wafer is ascertained in advance, and wet etching is performed by discharging an etchant liquid L1 at a thick portion of the film for processing; simultaneously with the discharge of the etchant liquid L1, a diluting liquid L2 for the etchant liquid L1 is discharged at a thin portion of the film for processing.
    Type: Application
    Filed: May 5, 2004
    Publication date: January 6, 2005
    Inventors: Hayato Iwamoto, Kei Kinoshita, Hajime Ugajin
  • Patent number: 6818502
    Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: November 16, 2004
    Assignee: Sony Corporation
    Inventors: Tomoyuki Hirano, Hayato Iwamoto
  • Publication number: 20040209457
    Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.
    Type: Application
    Filed: February 6, 2004
    Publication date: October 21, 2004
    Inventors: Tomoyuki Hirano, Hayato Iwamoto
  • Patent number: 6777355
    Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: August 17, 2004
    Assignee: Sony Corporation
    Inventors: Toshiro Kisakibaru, Isao Honbori, Yasushi Kato, Toshikazu Suzuki, Hirohisa Koriyama, Hayato Iwamoto, Hitoshi Abe
  • Publication number: 20040102058
    Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.
    Type: Application
    Filed: November 20, 2003
    Publication date: May 27, 2004
    Inventors: Toshiro Kisakibaru, Isao Honbori, Yasushi Kato, Toshikazu Suzuki, Hirohisa Koriyama, Hayato Iwamoto, Hitoshi Abe
  • Publication number: 20040081924
    Abstract: A resist stripping composition capable of reliably stripping off resist residue or polymer residue and keeping damage to the interconnects to a minimum and a method of producing a semiconductor device using the same, where the resist stripping composition comprises a salt of hydrofluoric acid and a base not including a metal, an organic solvent, a sugar alcohol such as xylitol, and water and has a hydrogen ion concentration of at least 8.
    Type: Application
    Filed: August 4, 2003
    Publication date: April 29, 2004
    Inventors: Hayato Iwamoto, Ryuichi Kanamura, Ai Endou, Tomoko Suzuki, Toshitaka Hiraga
  • Patent number: 6712077
    Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: March 30, 2004
    Assignee: Sony Corporation
    Inventors: Tomoyuki Hirano, Hayato Iwamoto
  • Publication number: 20040038154
    Abstract: One example of a separation-material composition for a photo-resist according to the present invention comprises 5.0 weight % of sulfamic acid, 34.7 weight % of H2O, 0.3 weight % of ammonium 1-hydrogen difluoride, 30 weight % of N,N-dimethylacetamide and 30 weight % of diethylene glycol mono-n-buthyl ether. Another example of a separation-material composition for a photo-resist according to the present invention comprises 1-hydroxyethylidene-1, 3.0 weight % of 1-diphosphonic acid, 0.12 weight % of anmonium fluoride, 48.38 weight % of H2O and 48.5 weight % of diethylene glycol mono-n-buthl ether.
    Type: Application
    Filed: August 14, 2003
    Publication date: February 26, 2004
    Inventors: Masafumi Muramatsu, Hayato Iwamoto, Kazumi Asada, Tomoko Suzuki, Toshitaka Hiraga, Tetsuo Aoyama
  • Patent number: 6670290
    Abstract: A manufacturing apparatus for a semiconductor device comprises: a clean room for installing a plurality of semiconductor manufacturing and processing apparatuses; an external air cleaning device connected to a supply port of the clean room for supplying a cleaned-up outside air into the clean room; a common air duct section installed in the clean room; a first air cleaning and ventilating means connected to said common air duct section for cleaning and ventilating a part of the cleaned-up outside air to the common air duct section; individual air duct section branched off from the common air duct section and connected to each of said semiconductor manufacturing and processing apparatuses; and a second air cleaning and ventilating means interposed between the individual air duct section and each of the semiconductor manufacturing and processing apparatuses for cleaning and ventilating the air to be supplied to each of the semiconductor manufacturing and processing apparatuses.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: December 30, 2003
    Inventors: Toshiro Kisakibaru, Isao Honbori, Yasushi Kato, Toshikazu Suzuki, Hirohisa Koriyama, Hayato Iwamoto, Hitoshi Abe
  • Publication number: 20030109137
    Abstract: According to the present invention, a process for changing the form of a processed film is performed to planarize it before the processed film which is formed on a wafer is processed in a manufacturing process of a semiconductor device. As the process for changing the form of the processed film, there may be exemplified a single wafer type wet etching process. The compatibility of the processed film with processing means is taken into consideration and, for instance, the wet etching process is applied to the processed film so as to eliminate parts incompatible with the processing means, so that a distribution in-plane of the processed film is previously improved.
    Type: Application
    Filed: October 7, 2002
    Publication date: June 12, 2003
    Inventors: Hayato Iwamoto, Kei Kinoshita