Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.

Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.

Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.

Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.

Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.

Abstract: An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.

Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.

Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.

Abstract: The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.

Abstract: A semiconductor apparatus having a through via to be electrically coupled with a chip includes a latch memory cell configured to be electrically coupled with the through via and receive a signal transmitted through the through via, and output a stored signal to the through via.

Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.

Abstract: The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.

Abstract: A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.

Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.

Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.

Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.