Patents by Inventor Heat-Bit Park
Heat-Bit Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11373699Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.Type: GrantFiled: August 21, 2020Date of Patent: June 28, 2022Assignee: SK hynix Inc.Inventors: Dong Uk Lee, Ji Hwan Kim, Heat Bit Park
-
Patent number: 10991400Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.Type: GrantFiled: December 17, 2018Date of Patent: April 27, 2021Assignee: SK hynix Inc.Inventors: Heat-Bit Park, Ji-Hwan Kim, Dong-Uk Lee
-
Publication number: 20200388322Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.Type: ApplicationFiled: August 21, 2020Publication date: December 10, 2020Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Ji Hwan KIM, Heat Bit PARK
-
Patent number: 10790011Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.Type: GrantFiled: September 5, 2018Date of Patent: September 29, 2020Assignee: SK hynix Inc.Inventors: Dong Uk Lee, Ji Hwan Kim, Heat Bit Park
-
Patent number: 10748601Abstract: An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.Type: GrantFiled: September 11, 2018Date of Patent: August 18, 2020Assignee: SK hynix Inc.Inventors: Ji-Hwan Kim, Heat-Bit Park
-
Patent number: 10566266Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.Type: GrantFiled: February 22, 2018Date of Patent: February 18, 2020Assignee: SK hynix Inc.Inventors: Heat Bit Park, Ji Hwan Kim, Dong Uk Lee
-
Publication number: 20190371371Abstract: An integrated circuit includes: one or more first sections in which first to Nth data (where N is an integer equal to or greater than 2) corresponding to one command are transferred through one line; and two or more second sections in which the first to Nth data are serial-to-parallel converted in 1:N and transferred through N lines, wherein whenever the command is applied, the first to Nth data are transferred without being inverted or transferred after being inverted repeatedly in at least one second section among the two or more second sections.Type: ApplicationFiled: December 17, 2018Publication date: December 5, 2019Inventors: Heat-Bit PARK, Ji-Hwan KIM, Dong-Uk LEE
-
Publication number: 20190267076Abstract: An address and command generation circuit, and a semiconductor system are disclosed. The address and command generation circuit may include a column address generator configured to correct an error of a column address, generate an internal column address based on an uncorrected column address when the column address corresponds to a read command, and generate the internal column address based on the corrected column address when the column address corresponds to a write command.Type: ApplicationFiled: September 5, 2018Publication date: August 29, 2019Applicant: SK hynix Inc.Inventors: Dong Uk LEE, Ji Hwan KIM, Heat Bit PARK
-
Publication number: 20190198089Abstract: An integrated circuit chip includes: one or more couplers suitable for transferring data between stacked chips; one or more data nodes suitable for transferring data to a host; and one or more transfer circuits on a transfer path for transferring data between the one or more couplers and the one or more data nodes, wherein at least one transfer circuit among the one or more transfer circuits inverts a portion of the data which is transferred by the at least one transfer circuit.Type: ApplicationFiled: September 11, 2018Publication date: June 27, 2019Inventors: Ji-Hwan KIM, Heat-Bit PARK
-
Publication number: 20180374779Abstract: A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.Type: ApplicationFiled: February 22, 2018Publication date: December 27, 2018Applicant: SK hynix Inc.Inventors: Heat Bit PARK, Ji Hwan KIM, Dong Uk LEE
-
Patent number: 9520167Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.Type: GrantFiled: November 17, 2015Date of Patent: December 13, 2016Assignee: SK Hynix Inc.Inventor: Heat-Bit Park
-
Patent number: 9437259Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.Type: GrantFiled: September 17, 2015Date of Patent: September 6, 2016Assignee: SK Hynix Inc.Inventors: Heat-Bit Park, Kang-Seol Lee
-
Patent number: 9373373Abstract: The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.Type: GrantFiled: December 8, 2014Date of Patent: June 21, 2016Assignee: SK hynix Inc.Inventor: Heat Bit Park
-
Patent number: 9368167Abstract: A semiconductor apparatus having a through via to be electrically coupled with a chip includes a latch memory cell configured to be electrically coupled with the through via and receive a signal transmitted through the through via, and output a stored signal to the through via.Type: GrantFiled: February 25, 2014Date of Patent: June 14, 2016Assignee: SK hynix Inc.Inventor: Heat Bit Park
-
Publication number: 20160071562Abstract: The invention may include a semiconductor apparatus comprising: a first die configured to latch and output external input data according to a strobe signal, to detect a valid pulse from among pulses of the strobe signal, and to generate a valid signal; and a second die configured to write data transmitted from the first die in response to the valid signal.Type: ApplicationFiled: December 8, 2014Publication date: March 10, 2016Inventor: Heat Bit PARK
-
Publication number: 20160071564Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.Type: ApplicationFiled: November 17, 2015Publication date: March 10, 2016Inventor: Heat-Bit PARK
-
Patent number: 9263371Abstract: A semiconductor device includes a through electrode vertically passing through the semiconductor device; a metal pad electrically coupling the through electrode and an exterior; a data input block suitable for transferring a data signal to the metal pad in response to a write command; a through electrode storage block suitable for storing the data signal transferred through the metal pad; and a data output block suitable for outputting the data signal, which is stored in the through electrode storage block, to the exterior in response to a read command.Type: GrantFiled: June 12, 2014Date of Patent: February 16, 2016Assignee: SK HynixInventor: Heat-Bit Park
-
Publication number: 20160005443Abstract: A memory may include first to Nth cell arrays configured to include a plurality of memory cells and one or more first to Nth data input/output pads respectively corresponding to the first to Nth cell arrays, wherein the one or more first to Nth data input/output pads are configured to input/output data to/from the first to Nth cell arrays.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Inventors: Heat-Bit PARK, Kang-Seol LEE
-
Patent number: 9202802Abstract: A semiconductor apparatus with a through via includes a semiconductor chip and a through via formed by penetrating through the semiconductor chip. The system further includes a first metal layer connected to a portion of the through via at an end of the through via and a second metal layer connected to another portion of the through via at the end of the through via.Type: GrantFiled: February 25, 2014Date of Patent: December 1, 2015Assignee: SK Hynix Inc.Inventors: Heat Bit Park, Jong Chern Lee, Hong Gyeom Kim
-
Patent number: 9190130Abstract: A semiconductor memory device includes a first signal generation unit configured to sequentially generate first and second delay signals in response to a first column control signal, the first and second delay signals having reflected a delay time and a multiplied delay time selected from a plurality of delay times in correspondence with an arrangement location of a unit memory region, through data is input/output, respectively, and a second signal generation unit configured to generate a second column control signal delayed by the selected delay time as compared with the first column control signal, to determine an activation time point of the second column control signal in response to the first delay signal, and to determine a deactivation time point of the second column control signal in response to the second delay signal.Type: GrantFiled: December 17, 2012Date of Patent: November 17, 2015Assignee: SK Hynix Inc.Inventor: Heat-Bit Park