Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.

Abstract: A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively.

Abstract: A semiconductor memory apparatus includes, inter alia, a master chip and a plurality of slave chips. Each of the slave chips includes a plurality of banks. A first reception signal, a first timing signal, a bank address signal, and a slice selection signal to the slave chips may be provided by a master chip. The slave chips include a slice determining unit configured to compare the slice selection signal and a slice code and generate a slice enable signal, and a bank selecting unit configured to receive the bank address signal in response to the first reception signal and the slice enable signal and generate a bank enable signal in response to the bank address signal and the first timing signal.

Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank.

Abstract: The semiconductor apparatus includes a reference delay value check unit configured to receive a source signal and delay the source signal to generate a reference delay signal; a process delay value check unit configured to receive the source signal and delay the source signal to generate a process delay signal; and a signal generation unit configured to receive the reference delay signal and the process delay signal, receive an input signal, and variably delay the input signal based on the reference delay signal and the process delay signal to generate an output signal.

Abstract: A method for testing an integrated circuit includes simulating the integrated circuit and generating waveforms of signals at a plurality of nodes of the integrated circuit, generating a text file representing the signal waveforms by detecting a waveform change of the signals, and analyzing the text file.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A semiconductor memory apparatus includes: a read/write control unit configured to generate a write control signal and a read control signal using internal signals generated through separate signal paths in response to a write command and a read command respectively; and a plurality of ranks configured to perform a write operation or read operation according to the write control signal or the read control signal.

Abstract: A semiconductor memory apparatus having stacked first and second chips includes a first chip test signal generation unit disposed in the first chip and configured to generate a first chip test signal in response to a first chip compression data determination signal in a test mode, a second chip test signal generation unit disposed in the second chip and configured to generate a second chip test signal in response to a second chip compression data determination signal in the test mode, and a final data determination unit configured to generate a final test to signal in response to the first and second chip test signals in the test mode.

Abstract: A semiconductor memory device includes a burst pulse generation unit configured to store a burst length information signal in response to a first control signal and output the burst length information signal as a burst pulse signal in response to a second control signal; and an input/output(I/O) control unit configured to generate the first and second control signals in response to a read pulse signal and a latency signal, respectively.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.

Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus comprises: first and second memory banks located a predetermined distance from each other in a first direction; a common column selection control unit located at an outside region in the first and second memory banks in the first direction, and configured to commonly control access to column areas in the first and second memory banks and generate a column selection signal that controls data access to the corresponding memory cells in the first and second memory banks; a first data read/write unit configured to sense and amplify read data transferred from the first memory bank and transfer write data to the first memory bank; and a second data read/write unit configured to sense and amplify read data transferred from the second memory bank and transfer write data to the second memory bank.

Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: first and second memory banks located at a predetermined distance from each other; a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to corresponding memory cells in the first and second memory banks; and a column selection signal repeater inserted in the common column selection signal transmission line, and configured to transfer the column selection signal for controlling data access to the memory cell in the first memory bank. A transmission path of the column selection signal for controlling data access to the memory cell in the first memory bank is longer than that of the column selection signal for controlling data access to the memory cell in the second memory bank.

Abstract: A semiconductor memory apparatus is provided. The semiconductor memory apparatus includes: a plurality of memory banks disposed at a predetermined distance from each other in a first direction; a common column selection control unit disposed at an outside region of the plurality of memory banks in the first direction, and configured to commonly control access to column areas of the plurality of memory banks; and a common column selection signal transmission line configured to transfer a column selection signal for controlling data access to the corresponding memory cells of the plurality of memory banks. The common column selection control unit generates the column selection signal, and a delay length of the column selection signal is adjusted based on a length of a transmission path of the column selection signal.

Abstract: An integrated circuit verification device includes a trace-back unit having structure data of an integrated circuit to be verified, and configured to trace back nodes of the integrated circuit in a direction from an output node to an input node; and a state defining unit having data with respect to a target state of the output node of the integrated circuit, and configured to sequentially define states of back-traced nodes to satisfy the target state of the output node.

Abstract: A data strobe clock buffer of a semiconductor memory apparatus includes a buffering block configured to buffer an external data strobe clock signal in response to a buffer enable signal to generate an internal data strobe clock signal, a timing discriminating block configured to discriminate toggle timing of the internal data strobe clock signal in response to a burst start signal and a burst length signal to generate a timing discrimination signal, and an enable controlling block configured to generate the buffer enable signal in response to the timing discrimination signal.