Abstract: A substrate for a semiconductor package comprises a dielectric substrate, a circuit pattern, and an electromagnetic band gap (EBG) pattern. The circuit pattern is formed on a first surface of the dielectric substrate and is connected to ground via a ground connection. The electromagnetic band gap (EBG) pattern comprises a plurality of zigzag unit structures formed on a second surface of the dielectric substrate, wherein the second surface is formed on an opposite side of the dielectric substrate from the first surface; the zigzag unit structures are electrically connected to each other; and at least one of the zigzag unit structures is electrically connected to the ground connection.

Abstract: A semiconductor package comprises a package board and a plurality of semiconductor chips sequentially stacked on the package board. Each of the semiconductor chips comprises a semiconductor substrate and an open loop-shaped chip line formed on the semiconductor substrate. The open loop-shaped chip line has first and second end portions. The first and second end portions of the open loop-shaped chip lines are electrically connected to each other by connectors, and the connectors and the open loop-shaped chip lines constitute a spiral antenna.

Abstract: In one aspect, a differential signal transfer method is provided which includes converting 2M-1 original signals into 2M-1 differential signal pairs, where M is an integer of 2 or more, and wherein each pair consists of a first differential signal and a second differential signal having opposite phases, and transferring the 2M-1 differential signal pairs to 2M signal lines such that each of the 2M signal lines includes overlapping differential signals among the first differential signals and the second differential signals of the 2M-1 differential signal pairs.

Abstract: A tape distribution substrate comprises a plurality of distribution lines formed on a base film. In one embodiment, the distribution lines comprise data lines arranged in data line pairs, wherein each data line pair carries a data signal with two different polarities. The distance between the data lines in each data line pair becomes narrower as the data lines extend away from the base film. In another embodiment, the distribution lines comprise power distribution lines, each having a body portion including several holes, and divided into one or more sub-power distribution lines connected to the base film.

Abstract: A multi-path printed circuit board (PCB) comprising separate direct current (DC) and alternating current (AC) paths, and a power delivery system including the same are provided. The multi-path PCB comprises a plurality of planar layers, each comprising a metal layer, and a plurality of insulators interposed between the planar layers. The metal layers may have different conductivities. The power delivery system includes a power source, a semiconductor IC, and the multi-path PCB. The multi-path PCB is adapted to function as a power delivery path for delivering power from the power source to the semiconductor IC.

Abstract: The present invention relates to a semiconductor chip coolant path, a semiconductor package utilizing the semiconductor chip coolant path, and a cooling system for the semiconductor package. For effective dissipation of heat generated during semiconductor chip operation, a semiconductor chip having a coolant path formed through or adjacent to its backside and a semiconductor package utilizing the semiconductor chip are provided. In addition, a cooling system for the semiconductor package circulates a coolant through the coolant path within the semiconductor package to directly contact and cool the semiconductor chip.

Abstract: A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract: A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.

Abstract: An embodiment relates to a temperature measuring device using a matrix switch, and a semiconductor package. In another embodiment a cooling system may be included. A plurality of temperature sensors may be arranged on a surface of a semiconductor device. The matrix switch may select the temperature sensors by an address method to form a circuit that includes the selected temperature sensor. A measuring unit may receive an output signal of the selected temperature sensor to calculate the temperature at the selected temperature sensor.

Abstract: In one embodiment, a semiconductor package comprises a base frame and a lower semiconductor chip electrically coupled to the base frame. The lower semiconductor chip has a first bond pad formed on a top surface thereof. The package further includes an upper semiconductor chip overlying the lower semiconductor chip. The upper semiconductor chip has a third bond pad formed on a bottom surface thereof. The package comprises a first conductive bump and a second conductive bump jointly coupling the first bond pad to the third bond pad.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: A multi-chip package may be provided which may include a substrate, on which multiple substrate bonding pads may be formed and under which multiple terminals may be formed, first and second semiconductor chips, which may be deposited on the substrate, and a spacer, which may be formed between the first and second semiconductor chips to have at least power and ground pads. The spacer may be used as passive element, and the first and second semiconductor chips and the power and ground pads of the spacer may be electrically connected. The pads of the semiconductor chip which may be deposited on the spacer may also be electrically connected to substrate bonding pads via the pads which may be formed on the spacer.

Abstract: A multi-chip package, a semiconductor device used therein, and manufacturing method thereof are provided. The multi-chip package may include a substrate having a plurality of substrate bonding pads formed on an upper surface thereof, at least one first semiconductor chip mounted on the substrate, and at least one second semiconductor chip mounted on the substrate where the at least one first semiconductor chip may be mounted. The at least one second semiconductor chip may include at least one three-dimensional space so as to allow the at least one first semiconductor chip to be enclosed within the at least one three-dimensional space. The at least one three-dimensional space may be a cavity, a groove, or a combination thereof.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.