Abstract: A tape distribution substrate comprises a plurality of distribution lines formed on a base film. In one embodiment, the distribution lines comprise data lines arranged in data line pairs, wherein each data line pair carries a data signal with two different polarities. The distance between the data lines in each data line pair becomes narrower as the data lines extend away from the base film. In another embodiment, the distribution lines comprise power distribution lines, each having a body portion including several holes, and divided into one or more sub-power distribution lines connected to the base film.

Abstract: A substrate for a semiconductor package comprises a dielectric substrate, a circuit pattern, and an electromagnetic band gap (EBG) pattern. The circuit pattern is formed on a first surface of the dielectric substrate and is connected to ground via a ground connection. The electromagnetic band gap (EBG) pattern comprises a plurality of zigzag unit structures formed on a second surface of the dielectric substrate, wherein the second surface is formed on an opposite side of the dielectric substrate from the first surface; the zigzag unit structures are electrically connected to each other; and at least one of the zigzag unit structures is electrically connected to the ground connection.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

Abstract: A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

Abstract: Flip chip packages and methods of manufacturing the same are provided, the flip chip packages may include a package substrate, a semiconductor chip, conductive bumps, a ground pattern and an underfilling layer. The semiconductor chip may be over the package substrate. The conductive bumps may be between the semiconductor chip and the package substrate to electrically connect the semiconductor chip and the package substrate with each other. The ground pattern may ground one of the package substrate and the semiconductor chip. The underfilling layer may be between the package substrate and the semiconductor chip to surround the conductive bumps. The underfilling layer may have a diode selectively located between the ground pattern and the conductive bumps by electrostatic electricity applied to the underfilling layer to protect the semiconductor chip from the electrostatic electricity.

Abstract: A package circuit board having a reduced package size. The package circuit board may include a semiconductor substrate in place of a printed circuit board. The package circuit board may further include a microelectronic chip mounted on the semiconductor substrate, the microelectronic chip having at least one of active and passive elements formed on the semiconductor substrate semiconductor substrate.

Abstract: A semiconductor package includes a main substrate, a semiconductor chip having a first side and a second side, the first side of the semiconductor chip disposed on the main substrate and electrically connected to the main substrate, and a conductive network formed on the second side of the semiconductor chip.

Abstract: A semiconductor chip can include a semiconductor substrate, an input portion and an output portion. A circuit element can be formed in the semiconductor substrate. The input portion can be formed on the semiconductor substrate. The input portion can include a first input pad to receive an input signal from the outside and a second input pad spaced apart from the first input pad, the second input pad being electrically connected to the first input pad through an external connection line such that the second input pad inputs the input signal to the circuit element. The output portion can be formed on the semiconductor substrate. The output pad can include an output pad to output an output signal from the circuit element.

Abstract: An electronic device having an electrostatic discharge (ESD) protection device and methods of fabricating the same. The electronic device can include an electronic element to be protected from electrostatic discharge. The electronic element can be installed on a substrate. The substrate can include a ground electrode disposed on the substrate, and a first element electrode disposed at a different level from the ground electrode on the substrate to overlap a part of the ground electrode and to electrically connect to the electronic element installed to the substrate. A dielectric layer can be disposed between the ground electrode and the first element electrode, wherein the ground electrode, the first element electrode and the dielectric layer disposed therebetween constitute an electrostatic discharge (ESD) protection device.

Abstract: In a bonding configuration for a semiconductor device package, the bonding angles of the bonding wires are maintained within acceptable limits, without causing an increase in the chip die size, and without necessitating the use of the corner rule. In this manner, the occurrence of shorting between adjacent bonding wires can be mitigated or eliminated, and device net die count during fabrication can be increased.

Abstract: An adjustable-inductance (AI) filter, a tape distribution substrate including the filter, and a display panel assembly including the tape distribution substrate are provided. The adjustable-inductance (AI) filter includes a filter distribution line including first and second end portions each having a first line width, at least one repair pattern having a second line width and disposed between the first and second end portions, and at least one unit filter bank connected in parallel to the at least one repair pattern, respectively.

Abstract: A semiconductor package features a ring-shaped silicon decoupling capacitor that reduces simultaneous switching noise. The decoupling capacitor is fabricated on a substrate from silicon using a wafer fabrication process and takes the form of an annular capacitive structure that extends around a periphery of a substrate-mounted integrated circuit (IC). The decoupling capacitor has a reduced thickness on or below a chip level and takes the place of a conventional power/ground ring. Therefore, the decoupling capacitor can be disposed within the package without increasing the thickness and the size of the package. The decoupling capacitor may be coupled to various power pins, allowing optimum wire bonding, shortened electrical connections, and reduced inductance. Bonding wires connected to the decoupling capacitor have higher specific resistance, lowering the peak of the resonance frequency and thereby reducing simultaneous switching noise.

Abstract: The present invention relates to a semiconductor package having a conductive molding compound to prevent static charge accumulation. By using a conductive molding compound heat conductivity is also increased and heat generated by the semiconductor chip is more effectively dissipated externally. Additionally, the conductive compound blocks electromagnetic waves making possible an optimal semiconductor package satisfying the electromagnetic compatibility (EMC) and increasing the reliability of the semiconductor chip especially when processing high-speed signals.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: The present invention relates to a semiconductor chip coolant path, a semiconductor package utilizing the semiconductor chip coolant path, and a cooling system for the semiconductor package. For effective dissipation of heat generated during semiconductor chip operation, a semiconductor chip having a coolant path formed through or adjacent to its backside and a semiconductor package utilizing the semiconductor chip are provided. In addition, a cooling system for the semiconductor package circulates a coolant through the coolant path within the semiconductor package to directly contact and cool the semiconductor chip.

Abstract: Provided are a multi-ground shielding semiconductor package including analog and digital circuit blocks and capable of preventing a coupling problem between the analog and digital circuit blocks caused by high frequency noise. A method of fabricating the multi-ground shielding semiconductor package, and a method of preventing noise in the multi-ground shielding semiconductor package are also provided. The multi-ground shielding semiconductor package includes at least one semiconductor chip; and a circuit board on which the semiconductor chip is mounted and on which a plurality of circuit blocks are formed, wherein a conductive ground shielding is formed between the circuit blocks and separately from grounds of the circuit blocks to prevent noise between the circuit blocks.

Abstract: A semiconductor package includes a chip including a conductive pattern thereon, a conductive network attached on a surface of the chip to absorb static electricity, at least one conductive rod attached to the conductive network, wherein the at least one conductive rod is formed substantially perpendicularly to the conductive network, and a grounding portion discharging the static electricity absorbed from the conductive network.

Abstract: A semiconductor package and testing method is disclosed. The package includes a substrate having top and bottom surfaces, a semiconductor chip mounted in a centrally located semiconductor chip mounting area of the substrate, and a plurality of test pads disposed on top and bottom surfaces of the substrate and comprising a first group of test pads configured on the top and bottom surfaces of the substrate and having a first height above the respective top and bottom surface of the substrate, and a second group of test pads disposed on the lower surface of the substrate and having a second height greater than the first, wherein each one of the second group of test pads includes a solder ball attached thereto.

Abstract: A printed circuit board for a high-speed semiconductor package uses bonding wires as a shield structure, e.g., to shield an open portion of signal transmission lines, and thereby reduce the likelihood of coupling noises, e.g., between signal transmission lines.

Abstract: A multi-chip package, a semiconductor device used therein, and manufacturing method thereof are provided. The multi-chip package may include a substrate having a plurality of substrate bonding pads formed on an upper surface thereof, at least one first semiconductor chip mounted on the substrate, and at least one second semiconductor chip mounted on the substrate where the at least one first semiconductor chip may be mounted. The at least one second semiconductor chip may include at least one three-dimensional space so as to allow the at least one first semiconductor chip to be enclosed within the at least one three-dimensional space. The at least one three-dimensional space may be a cavity, a groove, or a combination thereof.