Abstract: In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.

Abstract: An apparatus is described that includes a semiconductor chip memory array having resistive storage cells. The apparatus also includes a comparator to compare a first word to be written into the array against a second word stored in the array at the location targeted by a write operation that will write the first word into the array. The apparatus also includes circuitry to iteratively write to one or more bit locations where a difference exists between the first word and the second word with increasing write current intensity with each successive iteration.

Abstract: A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU. The second register is separate from the first register.

Abstract: In one embodiment, a device containing sensitive information may be placed in a data security mode. In such a data security mode, certain activities may trigger the partial or full erasure of the sensitive date before the data can be retrieved by an unauthorized user. In one embodiment, the data security mode may be a “park” mode in which unauthorized physical movement of the device triggers the partial or full erasure of the sensitive data stored in a nonvolatile memory before the data can be retrieved by an unauthorized user. In another aspect of the present description, the earth's magnetic field may be used to detect movement of a device in the park mode, and may be used to power the erasure of sensitive data as the device is moved relative to the earth's magnetic field. Other aspects are described herein.

Abstract: One aspect of the present description provides for automatically erasing at least a portion of a memory such as a nonvolatile memory, for example, of a device in response to a detected event such as a power shutdown or power-up process, for example. In one embodiment, an on-board erasure assistance device such as an electro-magnet, for example, facilitates sensitive data erasure. In accordance with another aspect of the present description, a satisfactory level of sensitive data erasure may be achieved by resetting a portion of the bits of the sensitive data, instead of resetting all the bits of sensitive data. In one embodiment, the bits which are reset to erase sensitive data may be randomly distributed over a subarray. Other aspects are described herein.

Abstract: Apparatus, systems, and methods for write operations in spin transfer torque (STT) memory are described. In one embodiment, a memory comprises at least one spin-transfer torque (STT) memory device, temperature sensor proximate the STT memory device and a controller comprising logic, at least partially including hardware logic, to monitor an output of the temperature sensor, implement a first write operation protocol when the output of the temperature sensor fails to exceed a threshold temperature, and implement a second write operation protocol when the output of the temperature sensor exceeds the threshold temperature. Other embodiments are also disclosed and claimed.

Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

Abstract: A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.

Abstract: In one embodiment, a magnetoresistance random access memory (MRAM) such as a spin transfer torque (STT) random access memory (RAM), for example, has a subarray of bitcells and an electro-magnet positioned adjacent the subarray. A magnetic field is directed through a ferromagnetic device of bitcells of the first subarray to assist in the changing of states of bitcells of the subarray from a first state to a second state in which the ferromagnetic device of the bitcell is changed from one of parallel and anti-parallel polarization to the other of parallel and anti-parallel polarization. Accordingly, the content of the subarray may be readily preset or erased to one of the parallel or anti-parallel state with assistance from an electro-magnet. During a normal write operation, the bits to the other state are written. Other aspects are described herein.

Abstract: In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.

Abstract: In a memory device where writing a memory cell to a first bit state takes longer than writing to the second bit state, selectively executing the write operation can amortize the performance cost of writing the bit state that takes longer to write. Write logic dequeues multiple cachelines from a write buffer and sets all bits of all cachelines to the first bit state in a single write operation. The write logic then executes separate write operations on each cacheline separately to selectively write memory cells of each respective cacheline to the second bit state.

Abstract: A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value.

Abstract: An apparatus and method for scrubbing spin transfer torque (STT) memory. For example, one embodiment of a apparatus comprises: a memory subsystem including at least one spin transfer torque (STT) memory, the STT memory arranged into one or more entries; and a scrub engine to ensure that the entries of the STT contain valid data, the scrub engine including analysis and processing logic to determine, for each entry, whether a specified scrubbing interval has expired and, if so, then to invalidate the entry or re-fetch data for the entry from a source and, if the scrubbing interval has not expired, then to perform error detection and/or correction on the entry.

Abstract: In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.

Abstract: A mechanism for recycling error bits in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprising a floating point unit (FPU) to generate a result value from applying an operation on floating point number inputs to the FPU and generate an error value using the result value. The FPU also writes the result value to a first register of the processing device dedicated to storing results from the operation of the FPU and writes the error value to a second register of the processing device dedicated to storing errors from the operation of the FPU.

Abstract: A method, device and system for representing numbers in a computer including storing a floating-point number M in a computer memory; representing the floating-point number M as an interval with lower and upper bounds A and B when it is accessed by using at least two floating-point numbers in the memory; and then representing M as an interval with lower and upper bounds A and B when it is used in a calculation by using at least three floating-point numbers in the memory. Calculations are performed using the interval and when the data is written back to the memory it may be stored as an interval if the size of the interval is significant, i.e. larger than a first threshold value. A warning regarding the suspect accuracy of any data stored as an interval may be issued if the interval is too large, i.e. larger than a second threshold value.

Abstract: In one embodiment, the present invention includes a method for generating a hybrid error correction code for a data block. The hybrid code, which may be a residual arithmetic-Hamming code, includes a first residue code based on the data block and a first parity code based on the data block and a Hamming matrix. Then the generated code along with the data block can be communicated through at least a portion of a datapath of a processor. Other embodiments are described and claimed.

Abstract: Generally, this disclosure provides error management across hardware and software layers to enable hardware and software to deliver reliable operation in the face of errors and hardware variation due to aging, manufacturing tolerances, etc. In one embodiment, an error management module is provided that gathers information from the hardware and software layers, and detects and diagnoses errors. A hardware or software recovery technique may be selected to provide efficient operation, and, in some embodiments, the hardware device may be reconfigured to prevent future errors and to permit the hardware device to operate despite a permanent error.

Abstract: A semiconductor chip is described having ECC decoder circuitry disposed along any of: i) an interconnect path that resides between an instruction execution core and a cache; ii) an interconnect path that resides between an instruction execution core and a memory controller; and, iii) an interconnect path that resides between a cache and a memory controller. The ECC decoder circuitry has an input register to receive data, CRC values associated with the data and residue information associated with the data.

Abstract: Embodiments of the invention relate to a mobile computing device with ambient energy harvesting capability. Embodiments of the invention, when manually operated by a user, convert the kinetic motion of a part of the user's hand, applied onto a controller of the device, to electrical energy. The energy can be used to power the device, or to charge the battery of the device. Embodiments of the invention include an electrical power storage device disposed in a housing, a display screen attached to the housing to display a plurality of user-interactive interfaces, and a manually operable input controller interactable with the interfaces and being coupled to an energy transformer in the housing to electrically charge the power storage device when operated.