Abstract: Semiconductor devices and methods of forming the same include forming a bottom source/drain structure around a fin. A multi-layer bottom spacer is formed on the bottom source/drain structure, around the fin. Each layer of the multi-layer bottom spacer has a respective vertical height above the bottom source/drain structure, with a layer of the multi-layer bottom spacer that is farthest from the fin having a greater vertical height than a layer that is closest to the fin, to address parasitic capacitance from the bottom source/drain structure.

Abstract: An approach forming semiconductor structure composed of a first plurality of vertical transport field-effect transistors in a lower semiconductor layer and a second plurality of vertical transport field-effect transistors in an upper semiconductor layer. The second plurality of vertical transport field-effect transistors is horizontally offset from the first plurality of vertical transport field-effect transistors by a horizontal distance that is one-half of a contacted gate pitch between adjacent vertical transport field-effect transistors in the same semiconductor layer.

Abstract: A semiconductor includes a semiconductor substrate having a bottom source/drain region and a vertical semiconductor fin having a bottom end that contacts the semiconductor substrate. The semiconductor device further includes a top source/drain region on a top end of the vertical semiconductor. The top source/drain region is separated from the semiconductor substrate by the vertical semiconductor fin. The semiconductor device further includes an electrically conductive cap on an outer surface of the top source/drain region.

Abstract: Embodiments of present invention provide a transistor structure. The transistor structure includes a first vertical fin of a first vertical transistor, the first vertical fin having a first and a second sidewall and a first and a second vertical end; a first bottom source/drain (S/D) region underneath the first vertical fin, wherein the first bottom S/D region having an edge that vertically aligns with the first vertical end of the first vertical fin; and a first gate stack surrounding the first vertical fin, wherein the first bottom S/D region horizontally extends beyond the first vertical fin, except at the edge of the first bottom S/D region that vertically aligns with the first vertical end of the first vertical fin, to have at least a portion vertically underneath the first gate stack. A method of manufacturing the transistor structure is also provided.

Abstract: Embodiments of present invention provide a method of forming a transistor structure. The method includes forming a set of vertical fins on top of a substrate; forming a conformal spacer lining the set of vertical fins and the substrate; forming sidewall spacers next to vertical portions of the conformal spacer; removing portions of the conformal spacer on top of the substrate and between the sidewall spacers; indenting the conformal spacer vertically between the sidewall spacers and the substrate to create openings; forming bottom spacers in the openings; and forming a shallow-trench-isolation (STI) structure between the bottom spacers. A structure formed thereby is also provided.

Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Abstract: A semiconductor device includes a first diffusion region having a first conductivity type, a first SiGe fin formed on the first diffusion region, a second diffusion region having a second conductivity type, and a second SiGe fin formed on the second diffusion region and including a central portion including a first amount of Ge, and a surface portion including a second amount of Ge which is greater than the first amount. A total width of the central portion and the surface portion is substantially equal to a width of the second diffusion region.

Abstract: A semiconductor structure including a dielectric isolation region between and electrical isolating a first top contact of a first stacked transistor from a second top contact of a second stacked transistor, where at least one vertical surface of the first top contact is substantially flush with at least one vertical surface of the isolation region, and where at least one vertical surface of the second top contact is substantially flush with the at least one vertical surface of the isolation region.

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a static random access memory (SRAM) cell. The SRAM cell may include a first section of the SRAM cell with a first pull-up transistor, first pull-down transistor, and first pass-gate transistor. The SRAM cell may include a second section of the SRAM cell with a second pull-up transistor, second pull-down transistor, and second pass-gate transistor. The first section of the SRAM cell and the second section of the SRAM cell may be arranged in a non-rectangular cell layout with the first pass-gate located at a first end of the non-rectangular cell layout and the second pass-gate at a second end of the non-rectangular cell layout opposite the first end.

Abstract: A vertical field effect transistor structure and method for fabricating the same. The structure includes a source/drain layer in contact with at least one semiconductor fin. An edge portion of the source/drain layer includes a notched region filled with a dielectric material. A spacer layer includes a first portion in contact with the source/drain layer and a second portion in contact with the dielectric material. A gate structure contacts the spacer layer and the dielectric material. The method includes forming a source/drain layer in contact with at least one semiconductor fin. A spacer layer is formed in contact with the source/drain layer. A portion of the spacer layer is removed to expose an end portion of the source/drain layer. The exposed end portion of the source/drain layer is recessed to form a notched region within the source/drain layer. A dielectric layer is formed within the notched region.

Abstract: A method of forming a transistor structure is provided. The method includes forming on a substrate first and second mandrels for forming two-dimensional (2D) transistor fin elements defining a pitch gap region, depositing and anisotropically etching back the first spacer material to form first and second spacers in and around the first and second mandrels, respectively, conformally depositing and anisotropically etching back second spacer material around the first and second spacers and in the pitch gap region to define space for forming an odd number of one-dimensional (1D) transistor fin elements in the pitch gap region and depositing and anisotropically etching back the first spacer material in the space with enough cycles to fill the space to form a third spacer.

Abstract: A semiconductor structure includes a semiconductor channel structure that has a body and a tip and a dielectric spacer adjacent to the tip. The tip is no less than 70% the thickness of the body.

Abstract: A semiconductor device comprises a substrate including at least one vertical fin extending from the substrate, a bottom source/drain region beneath the at least one vertical fin, a top source/drain region disposed above the at least one vertical fin, a metal gate structure, a contact coupled to the top source/drain region and first and second contact spacers disposed on each side of the contact.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.

Abstract: A semiconductor device includes a substrate, at least one semiconductor vertical fin extending from the substrate, a bottom source/drain region disposed beneath the at least one semiconductor vertical fin, and first and second isolation regions on respective longitudinal sides of the semiconductor vertical fin. Each of the first and second isolation regions extend vertically above the bottom source/drain region. A bottom spacer is disposed on the first and second isolation regions. A spacer segment of the bottom spacer is disposed on a first upper surface portion of the bottom source/drain region adjacent the first isolation region. A dielectric liner underlies at least portions of the first and second isolation regions. A dielectric segment of the dielectric liner is disposed on a second upper surface portion of the bottom source/drain region adjacent the second isolation region. At least one functional gate structure is disposed on the semiconductor vertical fin.

Abstract: VFET devices having a robust gate extension structure using late gate extension patterning and self-aligned gate and source/drain region contacts are provided. In one aspect, a VFET device includes: at least one bottom source/drain region present on a substrate; at least one fin disposed on the at least one bottom source/drain region, wherein the at least one fin serves as a vertical fin channel of the VFET device; a gate stack alongside the at least one fin; a gate extension metal adjacent to the gate stack at a base of the at least one fin; a barrier layer that separates the gate extension metal from the gate stack; and at least one top source/drain region at a top of the at least one fin. A VFET device that includes multiple VFETs present on a substrate, and a method of forming a VFET device are also provided.

Abstract: An apparatus includes a fin, a gate, and a gate contact. A portion of the fin is disposed in a first layer. The gate is disposed in the first layer and adjacent to the fin. The gate contact is disposed on the gate and in a second layer, wherein the second layer is disposed on the first layer such that the gate contact is above the fin.

Abstract: A long channel field-effect transistor is incorporated in a semiconductor structure. A semiconductor fin forming a channel region is configured as a loop having an opening therein. A dielectric isolation region is within the opening. Source/drain regions epitaxially grown on fin end portions within the opening are electrically isolated by the isolation region. The source/drain regions, the isolation region and the channel are arranged as a closed loop. The semiconductor structure may further include a short channel, vertical transport field-effect transistor.

Abstract: A method includes forming a p-type field effect transistor region and an n-type field effect transistor region into a semiconductor substrate. The method implements a process flow to fabricate highly doped top source/drains with minimal lithography and etching processes. The method permits the formation of VFETs with increased functionality and reduced scaling.