Patents by Inventor Hemanth Jagannathan

Hemanth Jagannathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GATE STACK RELIABILITY IN VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS
    Publication number: 20200058766
    Abstract: A semiconductor structure and a method for fabricating the same. The semiconductor structure includes at least one semiconductor fin. A first source/drain contacts the semiconductor fin. An interfacial layer contacts sidewalls of the semiconductor fin. An insulating layer contacts the interfacial layer. One or more conductive gate layers encapsulate the interfacial and insulating layers. A second source/drain is formed above the first source/drain. The method comprises forming at least one semiconductor fin. An interfacial layer is formed in contact with sidewalls of the semiconductor fin. An insulating layer is formed in contact with the interfacial layer. The interfacial layer and the insulating layer are encapsulated by one or more conductive gate layers.
    Type: Application
    Filed: August 17, 2018
    Publication date: February 20, 2020
    Inventors: Choonghyun LEE, Christopher J. WASKIEWICZ, Miaomiao WANG, Hemanth JAGANNATHAN
  • Vertical transport field-effect transistor including dual layer top spacer
    Patent number: 10559672
    Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a multi-layer top spacer that includes an oxygen barrier layer beneath a top dielectric layer. Techniques for fabricating the transistor include depositing the oxygen barrier layer over the gate stack prior to depositing the top dielectric layer. The oxygen barrier layer blocks oxygen diffusion during deposition of the top dielectric layer, thereby avoiding damage to underlying interfacial and gate dielectric layers.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Choonghyun Lee, Alexander Reznicek, Christopher Waskiewicz
  • Vertical transport field-effect transistor including air-gap top spacer
    Patent number: 10559671
    Abstract: A vertical transport field-effect transistor includes a top source/drain region separated from an underlying gate stack by a top spacer including open gaps to reduce capacitance therebetween. Techniques for fabricating the transistor include using a sacrificial spacer that is selectively removed prior to growth of the top source/drain region. The top source/drain region may be confined by opposing dielectric layers.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: February 11, 2020
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Choonghyun Lee, Alexander Reznicek, Christopher Waskiewicz
  • Multi-metal dipole doping to offer multi-threshold voltage pairs without channel doping for highly scaling CMOS device
    Patent number: 10546787
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • Semiconductor device and method of forming the semiconductor device
    Patent number: 10541239
    Abstract: A semiconductor device includes a first SiGe fin formed on a substrate and including a first amount of Ge, and a second SiGe fin formed on a substrate and including a central portion including a second amount of Ge, and a surface portion comprising a third amount of Ge which is greater than the second amount.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: January 21, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robin Hsin-Ku Chao, Hemanth Jagannathan, ChoongHyun Lee, Chun Wing Yeung, Jingyun Zhang
  • MULTI-METAL DIPOLE DOPING TO OFFER MULTI-THRESHOLD VOLTAGE PAIRS WITHOUT CHANNEL DOPING FOR HIGHLY SCALING CMOS DEVICE
    Publication number: 20200020594
    Abstract: A method for fabricating a semiconductor device including multiple pairs of threshold voltage (Vt) devices includes forming a stack on a base structure having a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices and a third region corresponding to a third pair of Vt devices. The stack includes a first dipole layer, a first sacrificial layer formed on the first dipole layer, a second sacrificial layer formed on the first sacrificial layer, and a third sacrificial layer formed on the second sacrificial layer. The method further includes forming a second dipole layer different from the first dipole layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE
    Publication number: 20200020539
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • FAST RECRYSTALLIZATION OF HAFNIUM OR ZIRCONIUM BASED OXIDES IN INSULATOR-METAL STRUCTURES
    Publication number: 20200020762
    Abstract: A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca21 or Pmn21. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Martin M. Frank, Kam-Leung Lee, Eduard A. Cartier, Vijay Narayanan, Jean Fompeyrine, Stefan Abel, Oleg Gluschenkov, Hemanth Jagannathan
  • MULTI-METAL DIPOLE DOPING TO OFFER MULTI-THRESHOLD VOLTAGE PAIRS WITHOUT CHANNEL DOPING FOR HIGHLY SCALING CMOS DEVICE
    Publication number: 20200020595
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Application
    Filed: September 25, 2019
    Publication date: January 16, 2020
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formation
    Patent number: 10535773
    Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 14, 2020
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Hemanth Jagannathan, Shogo Mochizuki, Gen Tsutsui, Chun-Chen Yeh
  • APPROACH TO CONTROL OVER-ETCHING OF BOTTOM SPACERS IN VERTICAL FIN FIELD EFFECT TRANSISTOR DEVICES
    Publication number: 20200013877
    Abstract: A method of forming a vertical fin field effect transistor device, including, forming one or more vertical fins with a hardmask cap on each vertical fin on a substrate, forming a fin liner on the one or more vertical fins and hardmask caps, forming a sacrificial liner on the fin liner, and forming a bottom spacer layer on the sacrificial liner.
    Type: Application
    Filed: August 28, 2019
    Publication date: January 9, 2020
    Inventors: Ruqiang Bao, Hemanth Jagannathan, Paul C. Jamison, ChoongHyun Lee
  • Formation of pure silicon oxide interfacial layer on silicon-germanium channel field effect transistor device
    Patent number: 10529573
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan
  • VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR STRUCTURE WITH SELF-ALIGNED TOP JUNCTION THROUGH EARLY TOP SOURCE/DRAIN EPITAXY
    Publication number: 20190393341
    Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 26, 2019
    Inventors: Shogo Mochizuki, Brent A. Anderson, Hemanth Jagannathan, Junli Wang
  • REDUCED STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE FOOT PRINT THROUGH CONTROLLED BOTTOM SOURCE/DRAIN PLACEMENT
    Publication number: 20190378767
    Abstract: A method of reducing the distance between co-linear vertical fin field effect devices is provided. The method includes forming a first vertical fin on a substrate, forming a second vertical fin on the substrate, and depositing a masking block in the gap between the first vertical fin and second vertical fin. The method further includes depositing a spacer layer on the substrate, masking block, first vertical fin, and second vertical fin, depositing a protective liner on the spacer layer, and removing a portion of the protective liner from the spacer layer on the masking block and substrate adjacent to the first vertical fin. The method further includes removing a portion of the spacer layer from a portion the masking block and a portion of the substrate adjacent to the first vertical fin, and growing a first source/drain layer on an exposed portion of the substrate and first vertical fin.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Inventors: Ruqiang Bao, Brent A. Anderson, Junli Wang, Kangguo Cheng, Choonghyun Lee, Hemanth Jagannathan
  • Silicon-germanium Fin structure having silicon-rich outer surface
    Patent number: 10504997
    Abstract: A semiconductor structure includes a substrate and a silicon-germanium (SiGe) fin formed on the substrate. The SiGe fin has a first portion having a first doping profile and a second portion having a second doping profile. The first portion of the SiGe fin has a Si-rich outer surface.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki, Koji Watanabe
  • MULTI-METAL DIPOLE DOPING TO OFFER MULTI-THRESHOLD VOLTAGE PAIRS WITHOUT CHANNEL DOPING FOR HIGHLY SCALING CMOS DEVICE
    Publication number: 20190371676
    Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
    Type: Application
    Filed: June 4, 2018
    Publication date: December 5, 2019
    Inventors: Ruqiang Bao, Vijay Narayanan, Terence B. Hook, Hemanth Jagannathan
  • FORMATION OF PURE SILICON OXIDE INTERFACIAL LAYER ON SILICON-GERMANIUM CHANNEL FIELD EFFECT TRANSISTOR DEVICE
    Publication number: 20190371611
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Application
    Filed: August 15, 2019
    Publication date: December 5, 2019
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, ChoongHyun Lee, Vijay Narayanan
  • Wrap-around-contact structure for top source/drain in vertical FETs
    Patent number: 10483361
    Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Christopher J. Waskiewicz, Alexander Reznicek, Hemanth Jagannathan
  • Vertical transistors having improved gate length control using uniformly deposited spacers
    Patent number: 10461172
    Abstract: Embodiments of the invention are directed to a method of forming a semiconductor device by forming a channel fin over a substrate, wherein the channel fin includes a plurality of channel fins, wherein a first spacing is defined between adjacent ones of a first set of the plurality of channel fins, wherein a second spacing is defined between adjacent ones of a second set of the plurality of channel fins, wherein the first spacing is not equal to the second spacing. An initial gate structure is formed over the plurality of channels. Formed along sidewalls of the initial gate structure are spacers that each has a predetermined spacer height, wherein a thickness of each of the spacers is insufficient to allow any one of the spacers to fill the first spacing or the second spacing. Portions of the initial gate structure that are not covered by the spacers are removed.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 29, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Christopher J. Waskiewicz, Hemanth Jagannathan, Yann Mignot, Stuart A. Sieg
  • Interface Charge Reduction for SiGe Surface
    Publication number: 20190326429
    Abstract: Techniques for interface charge reduction to improve performance of SiGe channel devices are provided. In one aspect, a method for reducing interface charge density (Dit) for a SiGe channel material includes: contacting the SiGe channel material with an Si-containing chemical precursor under conditions sufficient to form a thin continuous Si layer, e.g., less than 5 monolayers thick on a surface of the SiGe channel material which is optionally contacted with an n-dopant precursor; and depositing a gate dielectric on the SiGe channel material over the thin continuous Si layer, wherein the thin continuous Si layer by itself or in conjunction with n-dopant precursor passivates an interface between the SiGe channel material and the gate dielectric thereby reducing the Dit. A FET device and method for formation thereof are also provided.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: Devendra Sadana, Dechao Guo, Joel P. de Souza, Ruqiang Bao, Stephen w. Bedell, Shogo Mochizuki, Gen Tsutsui, Hemanth Jagannathan, Marinus Hopstaken