Patents by Inventor Heng-Wen Ting
Heng-Wen Ting has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11948999Abstract: A device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. The first semiconductor fin and the second semiconductor fin are over a substrate. The source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. The source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. The semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. A top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. The contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.Type: GrantFiled: July 26, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
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Publication number: 20240030317Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming a gate structure over a first portion of the semiconductor fin; etching a source/drain recess over a second portion of the semiconductor fin; and performing an in-situ source/drain etching and epitaxy process to form a source/drain epitaxial structure in the second portion of the semiconductor fin. The step of performing the in-situ source/drain etching and epitaxy process comprises performing a dry etching process to adjust a profile of the source/drain recess in a chamber; and after adjusting the dry etching process, epitaxially growing the source/drain epitaxial structure in the source/drain recess in the chamber.Type: ApplicationFiled: July 20, 2022Publication date: January 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Heng-Wen TING, Ming-Hua YU, Yee-Chia YEO, Han-Yu TANG
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Publication number: 20240021618Abstract: A method includes forming first devices in a first region of a substrate, wherein each first device has a first number of fins; forming second devices in a second region of the substrate that is different from the first region, wherein each second device has a second number of fins that is different from the first number of fins; forming first recesses in the fins of the first devices, wherein the first recesses have a first depth; after forming the first recesses, forming second recesses in the fins of the second devices, wherein the second recesses have a second depth different from the first depth; growing a first epitaxial source/drain region in the first recesses; and growing a second epitaxial source/drain region in the second recess.Type: ApplicationFiled: August 1, 2023Publication date: January 18, 2024Inventors: Chih-Yun Chin, Yen-Ru Lee, Chien-Chang Su, Yan-Ting Lin, Chien-Wei Lee, Bang-Ting Yan, Heng-Wen Ting, Chii-Horng Li, Yee-Chia Yeo
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Publication number: 20230352589Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Publication number: 20230343635Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.Type: ApplicationFiled: June 28, 2023Publication date: October 26, 2023Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
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Patent number: 11735664Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: GrantFiled: August 30, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Patent number: 11735668Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.Type: GrantFiled: July 28, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
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Patent number: 11728208Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.Type: GrantFiled: May 10, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Li-Li Su, Chien-Chang Su, Heng-Wen Ting, Jung-Chi Tai, Che-Hui Lee, Ying-Wei Li
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Publication number: 20230187540Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.Type: ApplicationFiled: February 6, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei Lee, Chii-Horng Li, Heng-Wen Ting, Yee-Chia Yeo, Yen-Ru Lee, Chih-Yun Chin, Chih-Hung Nien, Jing-Yi Yan
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Patent number: 11652105Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.Type: GrantFiled: January 7, 2021Date of Patent: May 16, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
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Patent number: 11575026Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.Type: GrantFiled: March 19, 2021Date of Patent: February 7, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei Lee, Chii-Horng Li, Heng-Wen Ting, Yee-Chia Yeo, Yen-Ru Lee, Chih-Yun Chin, Chih-Hung Nien, Jing-Yi Yan
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Publication number: 20220384437Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.Type: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
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Publication number: 20220376049Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.Type: ApplicationFiled: July 28, 2022Publication date: November 24, 2022Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
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Publication number: 20220359733Abstract: A device includes a first semiconductor fin, a second semiconductor fin, a source/drain epitaxial structure, a semiconductive cap, and a contact. The first semiconductor fin and the second semiconductor fin are over a substrate. The source/drain epitaxial structure is connected to the first semiconductor fin and the second semiconductor fin. The source/drain epitaxial structure includes a first protruding portion and a second protruding portion aligned with the first semiconductor fin and the second semiconductor fin, respectively. The semiconductive cap is on and in contact with the first protruding portion and the second protruding portion. A top surface of the semiconductive cap is lower than a top surface of the first protruding portion of the source/drain epitaxial structure. The contact is electrically connected to the source/drain epitaxial structure and covers the semiconductive cap.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ru LEE, Chii-Horng LI, Chien-I KUO, Heng-Wen TING, Jung-Chi TAI, Lilly SU, Yang-Tai HSIAO
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Patent number: 11482620Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.Type: GrantFiled: March 8, 2021Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
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Publication number: 20220302281Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a fin structure over the substrate, a gate structure over the fin structure, an epitaxial region formed in the fin structure and adjacent to the gate structure. The epitaxial region can embed a plurality of clusters of dopants.Type: ApplicationFiled: March 19, 2021Publication date: September 22, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei LEE, Chii-Horng LI, Heng-Wen TING, Yee-Chia YEO, Yen-Ru LEE, Chih-Yun CHIN, Chih-Hung NIEN, Jing Yi YAN
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Patent number: 11430878Abstract: A method includes etching a semiconductor substrate to form a plurality of semiconductor fins. The semiconductor fins are etched to form a recess. An epitaxy structure is grown in the recess. The epitaxy structure has a W-shape cross section. A capping layer is formed over the epitaxy structure. The capping layer is at least conformal to a sidewall of the epitaxy structure. The capping layer is etched to expose a top surface of the epitaxy structure. A first portion of the capping layer remains over the sidewall of the epitaxy structure after etching the capping layer. A contact is formed in contact with the exposed top surface of the epitaxy structure and the first portion of the capping layer.Type: GrantFiled: August 14, 2020Date of Patent: August 30, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yen-Ru Lee, Chii-Horng Li, Chien-I Kuo, Heng-Wen Ting, Jung-Chi Tai, Lilly Su, Yang-Tai Hsiao
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Publication number: 20220059655Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
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Publication number: 20220028856Abstract: A method includes forming a gate stack on a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to form a recess, and forming a source/drain region starting from the recess. The formation of the source/drain region includes performing a first epitaxy process to grow a first semiconductor layer, wherein the first semiconductor layer has straight-and-vertical edges, and performing a second epitaxy process to grow a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are of a same conductivity type.Type: ApplicationFiled: January 7, 2021Publication date: January 27, 2022Inventors: Jung-Chi Tai, Yi-Fang Pai, Tsz-Mei Kwok, Tsung-Hsi Yang, Jeng-Wei Yu, Cheng-Hsiung Yen, Jui-Hsuan Chen, Chii-Horng Li, Yee-Chia Yeo, Heng-Wen Ting, Ming-Hua Yu
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Publication number: 20210391456Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: ApplicationFiled: August 30, 2021Publication date: December 16, 2021Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung