SOURCE/DRAIN REGIONS OF FINFET DEVICES AND METHODS OF FORMING SAME
A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium concentration that is smaller than the second germanium concentration.
This application is a continuation of U.S. Pat. Application No. 17/460,453, filed on Aug. 30, 2021, which is a divisional of U.S. Pat. Application No. 16/441,337, filed on Jun. 14, 2019, now U.S. Pat. No. 11,107,923, issued Aug. 31, 2021, each application is hereby incorporated herein by reference.
BACKGROUNDSemiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Various embodiments are discussed herein in a particular context, namely, forming epitaxial source/drain regions in an p-type FinFET transistor. However, various embodiments may be applied to other semiconductor devices/processes, such as planar transistors. In some embodiments, the epitaxial source/drain regions described herein includes a bottom layer of silicon germanium doped with boron. In some cases, an increased concentration of germanium in the bottom layer can block other dopants (e.g., boron) from diffusing into other regions of the FinFET, and a decreased concentration of boron can reduce the amount of boron that diffuses into other regions of the FinFET. The formation of a bottom layer in this manner can reduce leakage current of a FinFET. Additionally, the reduced leakage current allows for a deeper source/drain recess to be etched, which increases the overall volume of the epitaxial source/drain regions. By increasing the volume of the epitaxial source/drain regions, the turn-on current of a FinFET may be increased.
A gate dielectric layer 104 is along sidewalls and over a top surface of the fin 52, and a gate electrode 106 is over the gate dielectric layer 104. Source/drain regions 98 are disposed in opposite sides of the fin 52 with respect to the gate dielectric layer 104 and gate electrode 106.
Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs.
In
The substrate 50 has a region 50N and a region 50P. The region 50N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The region 50P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The region 50N may be physically separated from the region 50P (as illustrated by divider 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the region 50N and the region 50P.
In
The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins 52.
In
In
In
The process described with respect to
Still further, it may be advantageous to epitaxially grow a material in region 50N (e.g., an NMOS region) different from the material in region 50P (e.g., a PMOS region). In various embodiments, upper portions of the fins 52 may be formed from silicon-germanium (SixGe1-x, where x can be in the range of 0 to 1). For example, in some embodiments, portions of the fins 52 formed in region 50P may be formed from silicon germanium having a composition that is between about 10% and about 50% germanium. In other embodiments, upper portions of the fins 52 may be formed from silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.
Further in
In the embodiments with different well types, the different implant steps for the region 50N and the region 50P may be achieved using a photoresist or other masks (not shown). For example, a photoresist may be formed over the fins 52 and the STI regions 56 in the region 50N. The photoresist is patterned to expose the region 50P of the substrate 50, such as a PMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the region 50N, such as an NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 1E18 atoms/cm3, such as between about 1E16 atoms/cm3 and about 1E18 atoms/cm3. After the implant, the photoresist is removed, such as by an acceptable ashing process.
Following the implanting of the region 50P, a photoresist is formed over the fins 52 and the STI regions 56 in the region 50P. The photoresist is patterned to expose the region 50N of the substrate 50, such as the NMOS region. The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the region 50N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the region 50P, such as the PMOS region. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 1E20 atoms/cm3, such as a dopant concentration between about 1E17 atoms/cm3 and about 1E20 atoms/cm3. After the implant, the photoresist may be removed, such as by an acceptable ashing process.
After the implants of the region 50N and the region 50P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together.
In
In
Further in
After the formation of the gate seal spacers 80, implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above in
In
It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers 80 may not be etched prior to forming the gate spacers 86, yielding “L-shaped” gate seal spacers, spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using a different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers 80 while the LDD regions for p-type devices may be formed after forming the gate seal spacers 80.
As shown in
In
The first source/drain layer 90 may comprise any acceptable materials, such as any materials that are appropriate for p-type FinFETs. In some embodiments, the first source/drain layer 90 is formed from silicon germanium, which may be doped or undoped. In some embodiments, the first source/drain layer 90 is formed from silicon germanium having atomic percentage of germanium that is between about 10% and about 40%. In some embodiments, the outer regions of the first source/drain layer 90 (e.g., the regions near the fins 52 and substrate 50) may have a smaller concentration of germanium than the inner regions of the first source/drain layer 90. For example, in some embodiments, the outer regions of the first source/drain layer 90 may have an atomic concentration of germanium that is between about 10% and about 25%, and the inner regions of the first source/drain layer 90 may have an atomic concentration of germanium that is between about 25% and about 40%. In some embodiments, the concentration of germanium transitions smoothly between different regions. In some cases, germanium in the first source/drain layer 90 may block dopant diffusion within the first source/drain layer 90. Thus, increasing the concentration of germanium within the first source/drain layer 90 can reduce the amount of out-diffusion of dopants from within the epitaxial source/drain regions 98A to the fins 52 or substrate 50. Dopants diffusing from an epitaxial source/drain region into a fin or substrate can cause leakage that decreases device performance, particularly when the epitaxial source/drain region extends near or into the substrate. By using a higher concentration of germanium to reduce dopant diffusion, the epitaxial source/drain regions 98A may be formed extending into the substrate 50 without causing leakage that degrades device performance. In some cases, the use of germanium within the first source/drain layer 90 can reduce leakage by as much as about 15% to about 40%. In this manner, the recesses 88 may be etched deeper to increase the volume of the epitaxial source/drain regions 98A while reducing leakage effects.
In some embodiments, the first source/drain layer 90 may have a dopant concentration between about 1E19 atoms/cm3 and about 1E21 atoms/cm3. The first source/drain layer 90 may be doped by one or more suitable p-type impurities, such as boron, BF2, indium, or the like. The first source/drain layer 90 may be implanted with dopants using in situ doping during growth, or using a process similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. In some embodiments, the outer regions of the first source/drain layer 90 may have a smaller concentration of dopants than the inner regions of the first source/drain layer 90. For example, in some embodiments, the outer regions of the first source/drain layer 90 may have a concentration of dopants that is between about 1E19 atoms/cm3 and about 1E20 atoms/cm3, and the inner regions of the first source/drain layer 90 may have a concentration of dopants that is between about 1E20 atoms/cm3 and about 1E21 atoms/cm3. In some embodiments, the concentration of dopants transitions smoothly between different regions. In some cases, forming the first/source/drain layer 90 with a lower concentration of dopants can reduce the amount of dopants that diffuse into the fins 52 or substrate 50.
In
In
The third source/drain layer 94 may have surfaces raised from respective surfaces of the fins 52 and may have facets. Further, the epitaxial growth processes used to form the third source/drain layer 94 may cause adjacent third source/drain layers 94 to merge, as illustrated in
In some embodiments, the source/drain regions 98A formed in the fins 52 exert stress in the respective channel regions 58, thereby improving performance. The source/drain regions 98A are formed in the fins 52 such that each dummy gate 72 is disposed between respective neighboring pairs of the source/drain regions 98A. In some embodiments the source/drain regions 98A may extend into, and may also penetrate through, the fins 52. In some embodiments, the gate spacers 86 are used to separate the source/drain regions 98A from the dummy gates 72 by an appropriate lateral distance so that the source/drain regions 98A do not short out subsequently formed gates of the resulting FinFETs.
In
In
In
In
In
The gate electrodes 106 are deposited over the gate dielectric layers 104, respectively, and fill the remaining portions of the recesses 95. The gate electrodes 106 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode 106 is illustrated in
The formation of the gate dielectric layers 104 in the region 50N and the region 50P may occur simultaneously such that the gate dielectric layers 104 in each region are formed from the same materials, and the formation of the gate electrodes 106 may occur simultaneously such that the gate electrodes 106 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 104 in each region may be formed by distinct processes, such that the gate dielectric layers 104 may be different materials, and/or the gate electrodes 106 in each region may be formed by distinct processes, such that the gate electrodes 106 may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes.
In
In
In some cases, forming a deeper source/drain recess in the fin of a FinFET device allows for a larger volume of the epitaxial source/drain regions, which can improve the turn-on current of the FinFET device. For example, in some cases a source/drain recess that extends through the fin and into the substrate can increase the turn-on current by as much as about 10%. However, source/drain regions that extend deeper can also cause an increase in leakage from the source/drain regions into the fin or substrate due to dopant diffusion. In some cases, when forming a first layer of silicon germanium in a source/drain region, increasing the atomic percentage of germanium can reduce out-diffusion of dopants (e.g., boron) from the source/drain regions. Additionally, by decreasing the doping concentration of the first layer of silicon germanium can also reduce the amount of dopants that diffuse into the fins or substrate. In this manner, the leakage current due to dopant diffusion can be reduced by as much as 5%. Thus, by forming a first layer of silicon germanium as described, deeper source/drain recesses may be used, and the turn-on current may be increased without also increasing the leakage current of a FinFET device.
In accordance with an embodiment, a method includes forming a semiconductor fin over a semiconductor substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the semiconductor substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium concentration that is smaller than the second germanium concentration. In an embodiment, the first semiconductor material comprises boron-doped silicon germanium having a boron concentration between 1 × 1019 atoms/cm3 and 1 × 1021 atoms/cm3. In an embodiment, the second semiconductor material comprises boron-doped silicon germanium having a germanium concentration from 20 to 80 atomic percent. In an embodiment, the first semiconductor material is epitaxially grown having a thickness on the sidewalls of the first recess that is between 1 nm and 10 nm. In an embodiment, the recess extends into the substrate a distance between 0 nm and 10 nm. In an embodiment, the semiconductor fin includes silicon germanium. In an embodiment, the substrate includes doped silicon having a boron concentration between 1 × 1017 atoms/cm3 and 1 × 1020 atoms/cm3.
In accordance with an embodiment, a device includes a fin extending from a substrate, the fin having a top surface that is a first height from a top surface of the substrate, a gate stack over the fin, a source/drain region in the fin adjacent the gate stack and in the substrate, wherein a bottom surface of the source/drain region is below the top surface of the substrate and wherein a top surface of the source/drain region is above the top surface of the fin, the source/drain region including a first source/drain material including silicon germanium having a first concentration of germanium and a first concentration of boron, a second source/drain material over the first source/drain material, the second source/drain including silicon germanium having a second concentration of germanium and a second concentration of boron, wherein the second concentration of germanium is greater than the first concentration of germanium and wherein the second concentration of boron is greater than the first concentration of boron, and a third source/drain material over the second source/drain material, the third source/drain material including silicon germanium having a third concentration of germanium and a third concentration of boron. In an embodiment, the bottom surface of the source/drain region is at a depth of 0 nm to 10 nm below the top surface of the substrate. In an embodiment, the top surface of the fin is at a height of 30 nm to 70 nm above the top surface of the substrate. In an embodiment, the fin includes silicon germanium and the substrate includes silicon. In an embodiment, the fin has a concentration of germanium that is between 10 atomic percent and 50 atomic percent. In an embodiment, the first concentration of germanium is between 10 atomic percent and 40 atomic percent. In an embodiment, the first concentration of boron is between 1 × 1019 atoms/cm3 and 1 × 1021 atoms/cm3. In an embodiment, the second concentration of boron is 10 times the first concentration of boron.
In accordance with an embodiment, a method includes forming a fin extending from a substrate, the fin having a first height above a surface of the substrate, etching the fin to form an opening, wherein the opening has a depth that is greater than the first height of the fin, and forming a source/drain region in the opening, wherein forming the source/drain region includes epitaxially growing a first semiconductor material in the opening, wherein a portion of the first semiconductor material extends below the surface of the substrate, wherein the first semiconductor material includes doped silicon germanium, epitaxially growing a second semiconductor material over the first semiconductor material, wherein the first semiconductor material includes doped silicon germanium having a greater dopant concentration and a greater atomic percent of germanium than the first semiconductor material, and epitaxially growing a third semiconductor material over the second semiconductor, wherein the third semiconductor material includes doped silicon germanium having a smaller dopant concentration and a smaller atomic percent of germanium than the second semiconductor material. In an embodiment, the depth of the opening is between 0 nm and 10 nm greater than the first height of the fin. In an embodiment, epitaxially growing the first semiconductor material includes growing the first semiconductor material to a thickness that is greater than a difference between the depth of the opening and the first height of the fin. In an embodiment, the first semiconductor material includes between 10 atomic percent and 40 atomic percent germanium and the first semiconductor material has a doping concentration that is between 1 × 1019 atoms/cm3 and 1 × 1021 atoms/cm3. In an embodiment, the first semiconductor material is doped with boron.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims
1. A device comprising:
- a first fin and a second fin extending from a substrate;
- an isolation region over the substrate, the isolation region being between the first fin and the second fin;
- a gate stack over the first fin and the isolation region;
- a first source/drain region in the first fin adjacent the gate stack and in the substrate, wherein a bottom surface of the first source/drain region is below a bottom surface of the isolation region, the first source/drain region comprising: a first source/drain material comprising silicon germanium having a first concentration of germanium and a first concentration of boron; a second source/drain material over the first source/drain material, the second source/drain material comprising silicon germanium having a second concentration of germanium and a second concentration of boron, wherein the second concentration of germanium is greater than the first concentration of germanium, wherein the second concentration of boron is greater than the first concentration of boron; and a third source/drain material over the second source/drain material, the third source/drain material comprising silicon germanium having a third concentration of germanium and a third concentration of boron.
2. The device of claim 1, wherein a thickness of the first source/drain material at a bottom of the first source/drain material is in a range between 3 nm and 20 nm.
3. The device of claim 1, further comprising:
- a second source/drain region having a same structure as the first source/drain region, wherein the third source/drain material extends continuously from over the second source/drain material of the first source/drain region to over the second source/drain material of the second source/drain region.
4. The device of claim 1, wherein an upper surface of the first source/drain material is higher than the bottom surface of the isolation region.
5. The device of claim 1, wherein an upper surface of the first source/drain material is higher than an upper surface of the second source/drain material.
6. The device of claim 1, wherein first source/drain material extends from an upper surface of a channel region to below the channel region.
7. The device of claim 1, wherein a distance between a bottom of the first source/drain material and the bottom surface of the isolation region is between 0 nm and 10 nm.
8. A device comprising:
- a first fin extending from a substrate;
- a gate stack over the first fin;
- a source/drain region adjacent the first fin under the gate stack, the source/drain region comprising: a first source/drain material comprising silicon germanium having a first concentration of germanium and a first concentration of boron, wherein the first source/drain material extends into the substrate; a second source/drain material over the first source/drain material, the second source/drain material comprising silicon germanium having a second concentration of germanium and a second concentration of boron, wherein the second concentration of germanium is greater than the first concentration of germanium, wherein the second concentration of boron is greater than the first concentration of boron, wherein the first source/drain material extends above the second source/drain material; and a third source/drain material over the second source/drain material, the third source/drain material comprising silicon germanium having a third concentration of germanium and a third concentration of boron, wherein the third source/drain material extends from the second source/drain material to above the first source/drain material.
9. The device of claim 8, wherein the third source/drain material contacts the first source/drain material and the second source/drain material.
10. The device of claim 8, wherein an upper surface of the second source/drain material is lower than an upper surface of the first fin.
11. The device of claim 8, wherein a thickness of the first source/drain material is in a range between 3 nm and 20 nm.
12. The device of claim 8, further comprising:
- a second fin, wherein the gate stack extends over the second fin;
- a fourth source/drain material comprising silicon germanium having the first concentration of germanium and the first concentration of boron, wherein the fourth source/drain material extends into the substrate; and
- a fifth source/drain material over the fourth source/drain material, the fifth source/drain material comprising silicon germanium having the second concentration of germanium and the second concentration of boron, wherein the third source/drain material extends over the second source/drain material and the fifth source/drain material.
13. The device of claim 8, wherein the substrate comprises a silicon substrate having an n-type dopant concentration between 1E16 atoms/cm3 and about 1E18 atoms/cm3, wherein the first source/drain material contacts the silicon substrate.
14. The device of claim 8, wherein the first concentration of germanium is between 10% and 40%.
15. The device of claim 14, wherein the second concentration of germanium is between 20% and 80%.
16. A device comprising:
- a fin extending from a substrate, the fin having a first height above a surface of the substrate, the fin having a recess, the recess having a depth greater than the first height of the fin; and
- a source/drain region in the recess, wherein the source/drain region comprises: a first semiconductor material in the recess, wherein a portion of the first semiconductor material extends below the surface of the substrate, wherein the first semiconductor material comprises doped silicon germanium; a second semiconductor material over the first semiconductor material, wherein the second semiconductor material comprises doped silicon germanium having a greater dopant concentration and a greater atomic percent of germanium than the first semiconductor material, wherein the first semiconductor material extends a greater height above the surface of the substrate than the second semiconductor material; and a third semiconductor material over the second semiconductor material, wherein the third semiconductor material comprises doped silicon germanium having a smaller dopant concentration and a smaller atomic percent of germanium than the second semiconductor material, wherein the third semiconductor material overlaps the first semiconductor material.
17. The device of claim 16, wherein the doped silicon germanium of the first semiconductor material has a dopant concentration in a range between 1×1019 atoms/cm3 and 1×1021 atoms/cm3.
18. The device of claim 17, wherein the doped silicon germanium of the first semiconductor material is doped with a p-type dopant.
19. The device of claim 16, wherein the first semiconductor material has a first p-type dopant concentration, the second semiconductor material has a second p-type dopant concentration, wherein the second p-type dopant concentration is 10 times the first p-type dopant concentration.
20. The device of claim 16, further comprising forming a contact to the source/drain region, wherein the contact extends through the third semiconductor material.
Type: Application
Filed: Jul 3, 2023
Publication Date: Nov 2, 2023
Patent Grant number: 12218240
Inventors: Kun-Mu Li (Zhudong Township), Heng-Wen Ting (Pingtung), Yen-Ru Lee (Hsinchu), Hsueh-Chang Sung (Zhubei City)
Application Number: 18/346,511