Abstract: One or more network nodes are configured for operation in a wireless communication network and, specifically, are configured to provide for co-existence between radar-scanning operations of a radar-enabled UE and network communications, where the radar transmissions are in a same or overlapping frequency range as regards the network communications. In an example implementation, a radio network node, referred to as an CONFIGURE ONE OR MORE access point or base station supports coexistence between radar sensing and network communications that are subject to interference from the radar sensing.

Abstract: A radar-enabled wireless communication device (12) is configured to communicate with a wireless communication network (10) and performs radar transmissions using a same or overlapping millimeter wave (mmW) frequency range, determine whether there are any neighboring wireless communication devices (32) that are vulnerable to interference from the radar transmissions and, if so, adapt radar transmissions in the affected radar beam directions or transmit assistance information enabling the vulnerable devices (32) to mitigate or avoid the interference. In a particular example, the wireless communication device (12) performs radar transmissions during a Downlink (DL) phase of the wireless communication network (10), such that the vulnerability determinations are with respect to DL interference at the neighboring wireless communication devices (32).

Abstract: A beamforming apparatus (10) performs beamforming via a plurality of antenna elements (12) by using per-branch sign reversal circuits (16) that approximate the per-branch phase values associated with a particular beam direction or shape by selectively reversing or not reversing the polarities of the individual branch signals (18). Eliminating continuous-valued or high-resolution phasing control from the branch circuits (14) that are fed into or from the respective antenna elements (12) simplifies the branch circuitry, thereby reducing the physical space needed for the branch circuits (14) and reducing loss and noise within the branch circuits (14). Further, operating the plurality of antenna elements (12) as two or more groups (24) and controlling the differential phase between the groups (24) advantageously reduces the errors arising from the approximation of the per-branch phase values.

Abstract: A wireless communications device that operates in a wireless communications system performs a radar function. This involves obtaining required radio frequency (RF) properties of a radar signal to be used for the radar function, wherein the radar function is one of a plurality of radar functions supported by the wireless communications device, each having a respective one of a plurality of different required RF properties. A transceiver of the wireless communications device is configured to transmit a predefined signal of the wireless communications system using time and frequency resources associated with the predefined signal of the wireless communications system and that satisfy the required RF properties of the radar signal. The configured transceiver is used to transmit the predefined signal of the wireless communications system.

Abstract: On-chip Multi-band equalizers for adjusting signal strength for a receiver receiving multi-band frequency signals are provided, The multi-band equalizer comprises multiple series connected tapped LC resonators. The tapped LC resonator may be capacitive tapping or inductive tapping, where both frequency and gain of the frequency bands of interest may be programmed by tuning the capacitances of the programmable capacitors and/or selecting the tapped out terminals of the inductors. The multi-band equalizer may be connected to a signal node, for instance between two amplifiers in the receiver.

Abstract: A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.

Abstract: A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.

Abstract: A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth.

Abstract: The present invention relates inter alia to a transmitter arrangement (1), in particular for radio communication, comprising at least two antenna elements (31, 32), spaced apart by a defined distance and a differential output amplifier (20) with a first output (21) coupled to a first (31) of the at least two antenna elements (31, 32) and with a second inverted output (22) coupled to a second (32) of the at least two antenna elements (31, 32). A first transmission line element (50) is arranged between at least one of the first and second outputs (21, 22) and the respective one of the at least two antenna elements (31, 32) and is configured such that signals applied to respective input taps (310, 320) of the at least two antenna elements (31, 32) are substantially in-phase with each other.

Abstract: A wireless communication node (500) and method therein for generating and transmitting a modulated radio frequency (RF) signal by means of backscattering are disclosed. The wireless communication node (500) comprises an antenna (510) configured to receive a illuminating RF signal, a switch (520) that has M states, a set of impedances (530) comprising Mimpedances (Z1, Z2 . . . ZM). The antenna (510) is coupled to the set of impedances (530) by the switch (520). The wireless communication node (500) further comprises a modulating value generator (540) configured to generate modulating values based on data to be transmitted and a frequency offset and a switch controller (550) configured to switch the state of the switch (520) based on the generated modulating values such that the antenna (510) is connected to a selected impedance among the M impedances.

Abstract: A time-to-digital converter (TDC) circuitry is disclosed for converting a phase difference between an input reference signal (109) and an input clock signal (110) to a digitally represented output signal (139). The TDC circuitry comprises a plurality of constituent TDC:s (101, 102, 103), a reference signal provider (120), and a digital signal combiner (130). Each constituent TDC is configured to convert a phase difference between a constituent reference signal (181, 182, 183) and a constituent clock signal (110) to a digitally represented constituent output signal (131, 132, 133). The reference signal provider (120) is configured to provide the respective constituent reference signals (181, 182, 183) to each of the constituent TDC:s (101, 102, 103).

Abstract: An oscillator circuit (15) is disclosed. It comprises N amplifier circuits (A1-A4), connected in a ring and has a first and a second supply terminal (s1, s2). Each amplifier circuit (A1-A4) comprises an input transistor (M1) having its gate connected to the input (in) of the amplifier circuit, its drain connected to an internal node (x) of the amplifier circuit, and its source connected to the first supply terminal (si). Furthermore, each amplifier circuit (A1-A4) comprises a first resonance circuit (R1) comprising a first inductor (Ls) and a first capacitor (Cs), wherein the first inductor (Ls) is connected between the internal node (x) and the output (out) of the amplifier circuit, and the first capacitor (Cs) is connected between the output (out) of the amplifier circuit and one of the first and the second supply terminals (s1, s2).

Abstract: A hybrid Phase Locked Loop, PLL (10, 34A, 34B, 38) employs an analog control loop during a first period of operation, such as steady-state operation, to achieve a simple design, stable operation at very high frequency, and low phase noise. During a second period of operation, such as frequency changes, a digital control loop takes over. Under digital control, charge pump (14) inputs are forced to be at or near 100% duty cycle for maximum loop filter (16) charging and fast, linear frequency change. The digital control loop monitors when the target frequency is reached, and exits the second period of operation with the proper feedback signal phase. The digital control loop can operate in two control modes. In a first mode, the phase of the divided VCO output signal is synchronized with the phase of a periodic reference signal throughout the frequency change.

Abstract: A Phase Locked Loop PLL circuit and method therein for generating multiphase output signals are disclosed. The PLL circuit includes a digitally controlled oscillator, a sample circuit, an analog to digital converter and a digital processing unit. The digital processing unit comprises a phase estimator configured to estimate a phase of the multiphase output signals, a differentiator configured to calculate a phase difference between a current phase and a previous phase, and an accumulator configured to accumulate the phase differences generated by the differentiator. The PLL circuit further comprises a loop filter configured to receive an output from the accumulator and generate a control signal to the digitally controlled oscillator to adjust frequency of the digitally controlled oscillator generating the multiphase output signals.

Abstract: An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (1051-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).

Abstract: A method performed in a base station for frequency calibration of a receiver is disclosed. The base station generates a first signal with periodic ASK modulation and transmits the first signal as a preamble or frequency marker signal to facilitate frequency calibration of the receiver. The receiver sweeps its oscillator frequency to detect if there is a preamble or frequency marker signal present. When it is determined that there is a signal present, the oscillator frequency of the receiver is calibrated to the transmitting frequency of the base station. The base station then transmits a second signal as a wakeup signal to the receiver.

Abstract: A circuit (100) for impedance transforming comprises a first port (P1), a second port (P2) and a tapped transformer (110) comprising a first winding (111) and a second winding (112). Each winding comprises a first terminal, a second terminal and a number of taps connected at different positions between the first and second terminals. The circuit (100) further comprises a first programmable capacitor (C1) connected in shunt with the first winding (111) and a second programmable capacitor (C2) connected in shunt with the second winding (112), a first set of switches (S1) connected between the number of taps on the first winding (111) and a terminal of the first port (P1), and a second set of switches (S2) connected between the number of taps on the second winding (112) and a terminal of the second port (P2).

Abstract: A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

Abstract: A plurality of Phase Locked Loops, PLL (12, 14), are distributed across an Integrated Circuit, each receiving a common reference signal (A). A local phase error (B) of each PLL (12, 14) is connected to a phase error averaging circuit (16), which calculates an average phase error (C), and distributes it back to each PLL (12, 14). In each PLL (12, 14), two loop filters (20, 22) with different bandwidths are deployed. A lower bandwidth, high DC gain, common mode loop operates on the average phase error, and forces the PLL outputs (H) to track the phase of the common reference signal. A high bandwidth, difference mode loop operates on the difference between the local phase error (B) and the average phase error (C) to suppress phase differences between PLL outputs, minimizing interaction between them. The reference noise contribution at the output is controlled by the common mode loop, which can have a low bandwidth.

Abstract: A method of a wireless transmitter is disclosed. The method is for mitigation of distortion caused by non-linear hardware components of the transmitter, wherein mitigation of distortion comprises mitigating at least one intermodulation component, wherein the transmitter is configured to process an input signal having an input signal spectrum, and wherein the transmitter comprises two or more signal branches, each signal branch comprising a respective non-linear hardware component. The method comprises modifying the input signal for a first one of the signal branches by applying a first phase shift to a first part of the input signal spectrum, wherein the first phase shift has a first sign and a first absolute value, and applying a second phase shift to a second part of the input signal spectrum. The second phase shift has a second sign which is opposite to the first sign, and a second absolute value which is equal to the first absolute value. The first and second parts are non-overlapping.