Abstract: A wireless device features a low-power, limited-functionality, narrowband, homodyne wakeup receiver with a free running local oscillator. This enables a very attractive combination of low power consumption and high selectivity. The network supports these receivers by adopting a wakeup message structure that supports oscillator frequency calibration, and that tolerates loss of parts of the signal spectrum. Wakeup signals are transmitted frequently to allow the wakeup receivers (whether targeted by a wakeup signal or not) to calibrate their LO frequencies. The frequencies of the wakeup signals can be constant, or follow a hopping pattern for increased immunity to interference. The wakeup signals can use multiple carriers to increase robustness to loss of parts of the signal spectrum, particularly near the LO frequency in a homodyne receiver. The carriers use amplitude modulation (OOK), with either different or equal sequences.

Abstract: A signal generator with direct digital synthesis and tacking filter to generate an oscillator signal. A digital signal generator generates a digital signal; a digital to analog converter is connected to an output of the digital signal generator and converts the digital signal to an analog signal; a filter is coupled to an output of the DAC and filters the analog signal and generates the oscillator signal; a comparator is coupled to an output of the filter and generates a signal indicating zero crossings of the filter output signal; a digital control unit is coupled to outputs of the digital signal generator and comparator and generates a control signal to tune the filter to track a center frequency of the generated oscillator signal. The control signal is generated based on adjacent samples values from the digital signal generator before and after zero crossings of the filter output signal.

Abstract: The disclosure relates to arrangements for antenna interfaces configurable to efficiently support different communication modes. This is achieved by an antenna connection circuit 10 for a communication device 1 wherein the antenna connection circuit 10 is configurable for communication modes. The antenna connection circuit comprises a first quarter-wave transformer qw1 coupled between an antenna port A and an transmitter port Tx, and a second quarter-wave transformer qw2 coupled between the antenna port A and a receiver port Rx. The antenna connection circuit further comprises a first ground switch s1 coupled between the receiver port Rx and a first ground connection g1, and a second ground switch s2 is coupled between the transmitter port Tx and a second ground connection g2.

Abstract: A method of a wireless transmitter is disclosed. The method is for mitigation of distortion caused by non-linear hardware components of the transmitter, wherein mitigation of distortion comprises mitigating at least one intermodulation component, wherein the transmitter is configured to process an input signal having an input signal spectrum, and wherein the transmitter comprises two or more signal branches, each signal branch comprising a respective non-linear hardware component. The method comprises modifying the input signal for a first one of the signal branches by applying a first phase shift to a first part of the input signal spectrum, wherein the first phase shift has a first sign and a first absolute value, and applying a second phase shift to a second part of the input signal spectrum. The second phase shift has a second sign which is opposite to the first sign, and a second absolute value which is equal to the first absolute value. The first and second parts are non-overlapping.

Abstract: The disclosure concerns controlling circuitry operably connectable to a plurality of constituent analog-to-digital converters (sub-ADCs) of an asynchronous time-interleaved analog-to-digital converter (TI-ADC). The controlling circuitry is configured to maintain a set of a number of sub-ADCs currently available for processing of an input sample, wherein the set is a subset of the plurality. Maintenance of the set is achieved by reception, from each of one or more of the sub-ADCs of the plurality, of an availability signal indicative of availability of the corresponding sub-ADC, and (responsive to the reception of the availability signal) addition of the corresponding sub-ADC to the set. Maintenance of the set is further achieved by (for each new input sample) selection of a sub-ADC of the set for processing of the new input sample, and (responsive to the selection) removal of the selected sub-ADC from the set and causing of the selected sub-ADC to process the new input sample.

Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

Abstract: A reference analog-to-digital converter (ADC) samples an input signal in parallel with sub-converters of a time-interleaved ADC. For each sub converter and for each of a plurality of output samples from the sub-converter, a calibration circuit determines whether the output sample from the sub-converter indicates an input signal polarity opposite that indicated by the reference ADC. For each such instance, a DC-offset sample is calculated as a difference between the output sample from the sub-converter and a target zero-crossing value for the sub-converter output. For each sub-converter, a series of DC-offset samples is filtered, to produce an average zero-crossing error for each sub-converter. This filtering may comprise a simple average, for example, or a moving average, a decaying filter, etc. Finally, a zero-crossing correction is applied for each of one or more of the sub-converters, based on the respective average zero-crossing error.

Abstract: A radio receiver comprises a local oscillator arrangement and a controller. The local oscillator arrangement is arranged to provide a signal for down-conversion of radio frequency signal to an intermediate frequency or a baseband frequency in the radio receiver, and the local oscillator arrangement is capable of selectably providing multiple frequency generation qualities. The controller is arranged to estimate a tolerable frequency generation quality for the current operation of the radio receiver or determine whether the current operation of the radio receiver is satisfactory in sense of a currently provided frequency generation quality, and based on the estimation or determination adjust frequency generation quality of the local oscillator arrangement by selecting one of the multiple frequency generation qualities. A radio arrangement, a method and a computer program are also disclosed.

Abstract: A switched capacitor arrangement for tuning a differential circuit is disclosed. The switched capacitor arrangement comprises a first node, a second node and a third node. The switched capacitor arrangement further comprises a first capacitor (C1) coupled between the first node and the second node, a second capacitor (C2) coupled between the second node and the third node, and a first switch branch comprising a first switch (S 1) coupled between the second node and a signal ground node. The first switch (S 1) has an on state and an off state. The first node and third node are configured to be connected to respective differential nodes (Vtank, ?Vtank) of the differential circuit. The switched capacitor arrangement is configured to tune the differential circuit by controlling the state of the first switch.

Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

Abstract: A radio receiver includes a local oscillator arrangement and a controller. The local oscillator arrangement is arranged to provide a signal for down-conversion of radio frequency signal to an intermediate frequency or a baseband frequency in the radio receiver, and the local oscillator arrangement is capable of selectably providing multiple frequency generation qualities. The controller is arranged to estimate a tolerable frequency generation quality for the current operation of the radio receiver or determine whether the current operation of the radio receiver is satisfactory in sense of a currently provided frequency generation quality, and based on the estimation or determination adjust frequency generation quality of the local oscillator arrangement by selecting one of the multiple frequency generation qualities. A radio arrangement, a method and a computer program are also disclosed.

Abstract: An integrated transformer arrangement for combining output signals of multiple differential power amplifiers to a single-ended load. The integrated transformer arrangement comprises a first transformer branch comprising an inductor loop. The inductor loop comprises a set of N windings connected in series. The first transformer branch further comprises a number of primary inductors. Each primary inductor comprises a winding placed concentrically to one winding of the inductor loop, and each primary inductor is configured to couple to a differential output of one of the multiple differential power amplifiers. The integrated transformer arrangement further comprises a secondary inductor comprising a winding placed concentrically to a winding of the inductor loop, and the secondary inductor is configured to couple to the single-ended load.

Abstract: A digital-to-analog conversion circuit (60) for converting a digital input sequence to an analog representation is disclosed. It comprises a first DAC, (100) wherein the first DAC (100) is of a capacitive voltage division type having a capacitive load (110). Furthermore, it comprises a second DAC (120) having a resistive load (130). An output (104) of the first DAC (100) and an output (124) of the second DAC (120) are connected, such that said capacitive load (110) and said resistive load (130) are connected in parallel.

Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), wherein the second feedback signal (FBD) is delayed with respect to the first feedback signal (FB). An interpolator is configured to receive the first and the second feedback signal (FB) and to provide an interpolated signal thereof between the first and second feedback signal and in response to a phase control word. A comparator path is configured to receive the interpolated signal and to provide a respective signal to the loop filter (1) in response to a phase deviation between a common reference signal (FR) and the interpolated signal.

Abstract: The disclosure relates to arrangements for antenna interfaces configurable to efficiently support different communication modes. This is achieved by an antenna connection circuit 10 for a communication device 1 wherein the antenna connection circuit 10 is configurable for communication modes. The antenna connection circuit comprises a first quarter-wave transformer qw1 coupled between an antenna port A and an transmitter port Tx, and a second quarter-wave transformer qw2 coupled between the antenna port A and a receiver port Rx. The antenna connection circuit further comprises a first ground switch s1 coupled between the receiver port Rx and a first ground connection g1, and a second ground switch s2 is coupled between the transmitter port Tx and a second ground connection g2.

Abstract: A radio receiver includes a local oscillator arrangement and a controller. The local oscillator arrangement is arranged to provide a signal for down-conversion of radio frequency signal to an intermediate frequency or a baseband frequency in the radio receiver, and the local oscillator arrangement is capable of selectably providing multiple frequency generation qualities. The controller is arranged to estimate a tolerable frequency generation quality for the current operation of the radio receiver or determine whether the current operation of the radio receiver is satisfactory in sense of a currently provided frequency generation quality, and based on the estimation or determination adjust frequency generation quality of the local oscillator arrangement by selecting one of the multiple frequency generation qualities. A radio arrangement, a method and a computer program are also disclosed.

Abstract: A phase locked loop, particularly for or in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), wherein the second feedback signal (FBD) is delayed with respect to the first feedback signal (FB). An interpolator is configured to receive the first and the second feedback signal (FB) and to provide an interpolated signal thereof between the first and second feedback signal and in response to a phase control word. A comparator path is configured to receive the interpolated signal and to provide a respective signal to the loop filter (1) in response to a phase deviation between a common reference signal (FR) and the interpolated signal.