Patents by Inventor Henry Chung

Henry Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040079984
    Abstract: A polysilicon self-alignment contact and a polysilicon common source line. A cell array formed on a semiconductor substrate has a second cell adjacent to a first cell in a Y-axis orientation, and a third cell adjacent to the first cell in an X-axis orientation. Each cell comprises a first gate structure and a second gate structure, a source region formed in the semiconductor substrate adjacent to the first gate structure and the second gate structure, and an opening formed between the first gate structure and the second gate structure to expose the source region. A drain region is formed in the semiconductor substrate adjacent to the second gate structure of the first cell and the first gate structure of the second cell. A contact hole is formed between the first cell and the second cell to expose the drain region. A polysilicon layer is formed in the contact hole to serve as a polysilicon self-aligned contact.
    Type: Application
    Filed: October 25, 2002
    Publication date: April 29, 2004
    Inventors: Hsuan-Ling Kao, Chun-Pei Wu, Hui-Huang Chen, Wen-Bin Tsai, Henry Chung
  • Patent number: 6713354
    Abstract: A method of manufacturing mask ROM is provided. A buried bit line is formed in a substrate and then a gate and a word line are formed over the substrate. Thereafter, a pre-coding layer with a plurality of pre-coding openings therein is formed over the substrate in a relatively high precision process. The pre-coding openings correspond in position to a plurality of coding regions on the substrate underneath the gate. A filler material is deposited into the pre-coding openings to form a filler layer. A coding mask having a plurality of coding openings is formed over the substrate in a relatively low precision process. The filler material inside the pre-coding openings that correspond in position to the code openings in the coding mask is removed. The coding mask is removed. Finally, a coding ion implant is carried out using the pre-coding layer and the filler layer as mask and hence ions are implanted into the code region through the pre-coding openings.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: March 30, 2004
    Assignee: Macronix International Co., Ltd.
    Inventor: Henry Chung
  • Publication number: 20030232509
    Abstract: A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 18, 2003
    Inventors: Chia-Chi Chung, Henry Chung, Ming-Chung Liang, Jerry Lai
  • Publication number: 20030205815
    Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure having a substrate, a layer of a first dielectric material on the substrate; and spaced apart metal contacts on the layer of the first dielectric material. There is a space between adjacent metal contacts and each space is filled with the first dielectric material. A recess is formed in the filled spaces of the first dielectric material which extends from a level at a top of the metal contacts a part of the distance toward the substrate. A second dielectric layer is on at least some of the metal contacts and in the recesses on the filled spaces of the first dielectric material such that there is optionally a gap in the recesses of the second dielectric layer at side walls of the metal contacts. An additional layer of the first dielectric material is on the second dielectric layer.
    Type: Application
    Filed: April 1, 2003
    Publication date: November 6, 2003
    Inventor: Henry Chung
  • Patent number: 6642139
    Abstract: A method for fabricating vias and trenches in a dual-damascene multilevel interconnection structure of an integration circuit is provided. The method uses chemical vapor deposition and flowfill dielectric technology to deposit a dielectric material at low temperature for fabricating interconnection structure in an integration circuit. It comprises the following steps: (a) forming photo-resist patterns; (b) depositing a dielectric layer at low temperature by chemical vapor deposition and flowfill dielectric technologies; (c) removing the dielectric layer by chemical-mechanical polishing to expose the photo-resist patterns; (d) removing the photo-resist patterns by chemical-mechanical polishing; and (e) stabilizing the dielectric layer by thermal curing.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: November 4, 2003
    Assignee: Macronix International Co., Ltd.
    Inventor: Henry Chung
  • Publication number: 20030181013
    Abstract: A fabrication method for a read only memory provides a substrate having a memory cell region and a periphery circuit region. A memory cell region has a memory cell array and the periphery circuit region has transistors. A precise layer having a plurality of first openings is formed in the memory cell region. The first openings are above the channel region of each memory cell in the memory cell array and the critical dimension of the first openings is identical. A mask layer having second openings and third openings is formed on the substrate. The second openings locate over a pre-coding memory cell region, and the third openings locate over the transistor gates. An ion implantation is performed to code the memory cell in the pre-coding memory cell region and to adjust the threshold voltage of the transistor, using the precise layer and the mask layer as a mask.
    Type: Application
    Filed: February 24, 2003
    Publication date: September 25, 2003
    Inventors: TAHORNG YANG, HENRY CHUNG, CHENG-CHEN CALVIN HSUEH, CHING-YU CHANG
  • Patent number: 6580275
    Abstract: An apparatus and method for determining the characteristic(s) of a discharge lamp (for example a fluorescent lamp or a high-intensity discharge lamp) operated by a high-frequency electronic ballast including a resonant tank that includes an inductor and a capacitor, wherein the characteristic(s) are selected from the group consisting of lamp input voltage, lamp resistance and lamp power, and including capability for measuring the inductor voltage and/or current, and capability for determining the characteristic(s) from the measured inductor voltage and/or current. More generally, the apparatus and method provide techniques for determining a number of parameters of a power converter circuit simply from measuring an inductor voltage or inductor current.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: June 17, 2003
    Assignee: City University of Hong Kong
    Inventors: Shu-Yuen Ron Hui, Shu-Hung Henry Chung
  • Patent number: 6559045
    Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: May 6, 2003
    Assignee: Alliedsignal Inc.
    Inventor: Henry Chung
  • Patent number: 6504247
    Abstract: A microelectronic device having a self aligned metal diffusion barrier is disclosed. A microelectronic device having a substrate and a dielectric layer on the substrate. A trench having inside walls is formed through the dielectric layer. A lining of a barrier metal is on the inside walls of the trench and a fill metal is in the trench between the linings on the inside walls of the trench. The fill metal and the barrier metal have substantially different removal selectivities. A covering of the barrier metal is on the fill metal and the covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: January 7, 2003
    Assignee: AlliedSignal Inc.
    Inventor: Henry Chung
  • Patent number: 6498399
    Abstract: The invention provides microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer and an additional layer of the first dielectric material positioned on the second dielectric material.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: December 24, 2002
    Assignee: AlliedSignal Inc.
    Inventors: Henry Chung, James Lin
  • Patent number: 6486615
    Abstract: The invention provides an apparatus and a method for controlling the power output of a fluorescent lamp in order to provide dimming control. The fluorescent lamp is driven by an electronic ballast, for example a half-bridge resonant inverter, and the electronic ballast is switched at a constant frequency and with a constant duty-cycle, but with a variable DC voltage power input. Dimming control is provided by variation of the DC voltage power supply. The variable DC supply may be obtained from an AC source followed by a power factor corrected AC-DC variable converter, or a DC source followed by a variable DC—DC converter.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: November 26, 2002
    Assignee: City University of Hong Kong
    Inventors: Shu-Yuen Ron Hui, Shu-Hung Henry Chung
  • Publication number: 20020158283
    Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.
    Type: Application
    Filed: June 12, 2002
    Publication date: October 31, 2002
    Inventor: Henry Chung
  • Patent number: 6472124
    Abstract: A fabrication method for a self-aligned metal-insulator-metal capacitor is described. A plurality of metal interconnects is provided. A metal interconnect is etched back to form a recess in the metal interconnect using a patterned photoresist as a mask. A capacitor insulator is formed on the resulting structure, partially filling the recess in the metal interconnect and covering other metal interconnects. A top electrode metal layer is then deposited on the capacitor insulator, completely filling the recess in the metal interconnect. The top electrode metal layer that is formed above the recess of the metal interconnect is subsequently removed.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: October 29, 2002
    Assignee: Macronix International Co., Ltd.
    Inventor: Henry Chung
  • Publication number: 20020142577
    Abstract: The invention provides microelectronic devices such as integrated circuit devices. Such have vias, interconnect metallization and wiring lines using dissimilar low dielectric constant intermetal dielectrics. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. A microelectronic device is formed having a substrate and a layer of a first dielectric material positioned on the substrate. A layer of a second dielectric material is positioned on the first dielectric layer and an additional layer of the first dielectric material positioned on the second dielectric material.
    Type: Application
    Filed: September 8, 1999
    Publication date: October 3, 2002
    Inventors: HENRY CHUNG, JAMES LIN
  • Publication number: 20020130416
    Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.
    Type: Application
    Filed: June 9, 1999
    Publication date: September 19, 2002
    Inventors: SHI-QING WANG, HENRY CHUNG, JAMES LIN
  • Patent number: 6452275
    Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderless via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: September 17, 2002
    Assignee: AlliedSignal Inc.
    Inventor: Henry Chung
  • Publication number: 20020113315
    Abstract: The invention relates to the formation of structures in microelectronic devices such as integrated circuit devices by means of borderiess via architectures in intermetal dielectrics. An integrated circuit structure has a substrate, a layer of a second dielectric material positioned on the substrate and spaced apart metal contacts are on the layer of the second dielectric material. The metal contacts have side walls, and a lining of a first dielectric on the side walls; a space between the linings on adjacent metal contact side walls filled with the second dielectric material, a top surface of each of the metal contacts, the linings and the spaces are at a common level. An additional layer of the second dielectric material is on some of the metal contacts, linings and filled spaces. At least one via extends through the additional layer of the second dielectric material and extends to the top surface of at least one metal contact and optionally at least one of the linings.
    Type: Application
    Filed: June 9, 1999
    Publication date: August 22, 2002
    Inventor: HENRY CHUNG
  • Publication number: 20020086487
    Abstract: A microelectronic device having a self aligned metal diffusion barrier is disclosed. A microelectronic device having a substrate and a dielectric layer on the substrate. A trench having inside walls is formed through the dielectric layer. A lining of a barrier metal is on the inside walls of the trench and a fill metal is in the trench between the linings on the inside walls of the trench. The fill metal and the barrier metal have substantially different removal selectivities. A covering of the barrier metal is on the fill metal and the covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.
    Type: Application
    Filed: January 29, 2002
    Publication date: July 4, 2002
    Inventor: Henry Chung
  • Patent number: 6403424
    Abstract: A method for forming a self-aligned mask read only memory by dual damascene trenches is disclosed. In the method, a thickness difference is formed between the gate area and periphery to be formed with a dual damascene trench so as to be formed with a condition of self-alignment of read only memory code. Thus, the manufacturing range in the lithography is enlarged, and an ion implantation process with self-aligned ability complete. Therefore, self-aligned read only memory codes and metal word lines are formed. The defect of disalignment in the read only memory code is resolved and the difficulty in the manufacturing process is reduced.
    Type: Grant
    Filed: October 2, 2001
    Date of Patent: June 11, 2002
    Assignee: Macronix International Co., Ltd.
    Inventors: Chung-Yeh Lee, Pei-Ren Jeng, Henry Chung
  • Patent number: 6395607
    Abstract: A microelectronic device having a self aligned metal diffusion barrier is disclosed. A microelectronic device having a substrate and a dielectric layer on the substrate. A trench having inside walls is formed through the dielectric layer. A lining of a barrier metal is on the inside walls of the trench and a fill metal is in the trench between the linings on the inside walls of the trench. The fill metal and the barrier metal have substantially different removal selectivities. A covering of the barrier metal is on the fill metal and the covering spans the linings on the inside walls of the trench and conforms to the top of the fill metal in the trench.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: May 28, 2002
    Assignee: AlliedSignal Inc.
    Inventor: Henry Chung