Patents by Inventor Henry Packard Moreton

Henry Packard Moreton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10424074
    Abstract: Methods and apparatuses are disclosed for reporting texture footprint information. A texture footprint identifies the portion of a texture that will be utilized in rendering a pixel in a scene. The disclosed methods and apparatuses advantageously improve system efficiency in decoupled shading systems by first identifying which texels in a given texture map are needed for subsequently rendering a scene. Therefore, the number of texels that are generated and stored may be reduced to include the identified texels. Texels that are not identified need not be rendered and/or stored.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 24, 2019
    Assignee: NVIDIA Corporation
    Inventors: Yury Uralsky, Henry Packard Moreton, Eric Brian Lum, Jonathan J. Dunaisky, Steven James Heinrich, Stefano Pescador, Shirish Gadre, Michael Alan Fetterman
  • Patent number: 10269090
    Abstract: One embodiment of the present invention includes techniques for processing a multi-resolution hierarchy, where an application configures a ROP unit to render all the levels included in the multi-resolution hierarchy to a single composite render target. The ROP unit renders memory pages to the composite render target in pitch order. In contrast, the texture unit accesses the composite render target with memory pages in pitch order for each level of the hierarchy. The application configures the MMU to ensure that the composite render target is correctly interpreted by the texture unit. Notably, the MMU translates ROP unit virtual addresses and texture unit virtual addresses using different mapping strategies to the same physical address space. One advantage of the disclosed embodiments is that rendering to the multi-resolution hierarchy does not require the CPU to execute the state parameter changes that are associated with rendering the different hierarchical levels using prior-art techniques.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: April 23, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Eric B. Lum, Henry Packard Moreton
  • Patent number: 10169072
    Abstract: A method for providing state inheritance across command lists in a multi-threaded processing environment. The method includes receiving an application program that includes a plurality of parallel threads; generating a command list for each thread of the plurality of parallel threads; causing a first command list associated with a first thread of the plurality of parallel threads to be executed by a processing unit; and causing a second command list associated with a second thread of the plurality of parallel threads to be executed by the processing unit, where the second command list inherits from the first command list state associated with the processing unit.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: January 1, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Jerome F. Duluk, Jr., Jesse David Hall, Henry Packard Moreton, Patrick R. Brown
  • Patent number: 10102668
    Abstract: A system, method, and computer program product are provided for rendering at variable sampling rates. Vertex coordinates for 3D primitive are received from a shader execution unit, and an arithmetic operation is performed on the vertex coordinates by fixed operation circuitry to produce modified vertex coordinates in homogeneous coordinate space. The modified vertex coordinates are transformed from homogeneous coordinate space into screen-space to produce screen-space vertex coordinates of a transformed 3D primitive and the transformed 3D primitive is rasterized in screen-space using the screen-space vertex coordinates to produce an image for display.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: October 16, 2018
    Assignee: NVIDIA Corporation
    Inventors: Henry Packard Moreton, Jonah M. Alben
  • Patent number: 10078911
    Abstract: A system, method, and computer program product are provided for executing processes involving at least one primitive in a graphics processor, utilizing a data structure. In operation, a data structure is associated with at least one primitive. Additionally, a plurality of processes involving the at least one primitive are executed in a graphics processor, utilizing the data structure. Moreover, the plurality of processes include at least one of selecting at least one surface or portion thereof to which to render, or selecting at least one of a plurality of viewports.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 18, 2018
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Yury Uralsky, Tyson Bergland, Eric Brian Lum, Jerome F. Duluk, Henry Packard Moreton
  • Patent number: 10068366
    Abstract: A method, computer readable medium, and system are disclosed for generating multi-view image data. The method includes the steps of processing primitive data of a model to generate processed primitive data that includes multiple position vectors for each vertex in the primitive data, the number of position vectors associated with each vertex being equal to the number of views in at least two views being generated. The method further includes storing the processed primitive data in a buffer. Finally, the processed primitive data may be read from the buffer for each view in the at least two views and transmitted to a raster pipeline to generate image data corresponding to a particular view.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: September 4, 2018
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff
  • Patent number: 9953455
    Abstract: Techniques are disclosed for storing post-z coverage data in a render target. A color raster operations (CROP) unit receives a coverage mask associated with a portion of a graphics primitive, where the graphics primitive intersects a pixel that includes a multiple samples, and the portion covers at least one sample. The CROP unit stores the coverage mask in a data field in the render target at a location associated with the pixel. One advantage of the disclosed techniques is that the GPU computes color and other pixel information only for visible fragments as determined by post-z coverage data. The GPU does not compute color and other pixel information for obscured fragments, thereby reducing overall power consumption and improving overall render performance.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 24, 2018
    Assignee: NVIDIA Corporation
    Inventors: Eric B. Lum, Rui Bastos, Jerome F. Duluk, Jr., Henry Packard Moreton, Yury Y. Uralsky
  • Patent number: 9947084
    Abstract: A technique for multiresolution consistent rasterization in which a setup unit calculates universal edge equations for a universal resolution. A rasterizer evaluates coverage data for two different resolutions based on the edge equations. The rasterizer evaluates coverage data for different effective pixel sizes—a large pixel size and a small pixel size. Optionally, the rasterizer may determine a first set of coverage data by performing conservative rasterization to determine coverage data for large pixels. Optionally, the rasterizer may then determine a second set of coverage data by performing standard rasterization for small pixels. Optionally, for the second set of coverage data, the rasterizer may evaluate only the small pixels that are within large pixels in the first set of coverage data that evaluate as covered.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 17, 2018
    Assignee: NVIDIA Corporation
    Inventors: Eric B. Lum, John S. Montrym, Walter R. Steiner, Justin Cobb, Henry Packard Moreton
  • Publication number: 20170323469
    Abstract: A method, computer readable medium, and system are disclosed for generating multi-view image data. The method includes the steps of processing primitive data of a model to generate processed primitive data that includes multiple position vectors for each vertex in the primitive data, the number of position vectors associated with each vertex being equal to the number of views in at least two views being generated. The method further includes storing the processed primitive data in a buffer. Finally, the processed primitive data may be read from the buffer for each view in the at least two views and transmitted to a raster pipeline to generate image data corresponding to a particular view.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 9, 2017
    Inventors: Ziyad Sami Hakura, Eric B. Lum, Henry Packard Moreton, Emmett M. Kilgariff
  • Publication number: 20170323475
    Abstract: A system, method, and computer program product are provided for rendering at variable sampling rates. Vertex coordinates for 3D primitive are received from a shader execution unit, and an arithmetic operation is performed on the vertex coordinates by fixed operation circuitry to produce modified vertex coordinates in homogeneous coordinate space. The modified vertex coordinates are transformed from homogeneous coordinate space into screen-space to produce screen-space vertex coordinates of a transformed 3D primitive and the transformed 3D primitive is rasterized in screen-space using the screen-space vertex coordinates to produce an image for display.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 9, 2017
    Inventors: Henry Packard Moreton, Jonah M. Alben
  • Patent number: 9767600
    Abstract: A graphics processing pipeline within a parallel processing unit (PPU) is configured to perform path rendering by generating a collection of graphics primitives that represent each path to be rendered. The graphics processing pipeline determines the coverage of each primitive at a number of stencil sample locations within each different pixel. Then, the graphics processing pipeline reduces the number of stencil samples down to a smaller number of color samples, for each pixel. The graphics processing pipeline is configured to modulate a given color sample associated with a given pixel based on the color values of any graphics primitives that cover the stencil samples from which the color sample was reduced. The final color of the pixel is determined by downsampling the color samples associated with the pixel.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: September 19, 2017
    Assignee: NVIDIA Corporation
    Inventors: Jeffrey A. Bolz, Mark J. Kilgard, Henry Packard Moreton, Rui M. Bastos, Eric B. Lum
  • Patent number: 9754407
    Abstract: A system, method, and computer program product are provided for shading using a dynamic object-space grid. An object defined by triangle primitives in a three-dimensional (3D) space that is specific to the object is received and an object-space shading grid is defined for a first triangle primitive of the triangle primitives based on coordinates of the first triangle primitive in the 3D space. A shader program is executed by a processing pipeline to compute a shaded value at a point on the object-space shading grid for the first triangle primitive.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: September 5, 2017
    Assignee: NVIDIA Corporation
    Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, Jr., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
  • Patent number: 9754561
    Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: September 5, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Jonathan Dunaisky, Henry Packard Moreton, Jeffrey A. Bolz, Yury Y. Uralsky, James Leroy Deming, Rui M. Bastos, Patrick R. Brown, Amanpreet Grewal, Christian Amsinck, Poornachandra Rao, Jerome F. Duluk, Jr., Andrew J. Tao
  • Patent number: 9747661
    Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: August 29, 2017
    Assignee: NVIDIA Corporation
    Inventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
  • Patent number: 9747718
    Abstract: A system, method, and computer program product are provided for performing object-space shading. A primitive defined by vertices in three-dimensional (3D) space that is specific to an object defined by at least the primitive is received and a shading sample rate is computed for the primitive based on a screen-space derivative of coordinates of a pixel fragment transformed into the 3D space. A shader program is executed by a processing pipeline to compute shaded attributes for the primitive according to the computed shading sample rate.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: August 29, 2017
    Assignee: NVIDIA Corporation
    Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, Jr., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
  • Patent number: 9659399
    Abstract: A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: May 23, 2017
    Assignee: NVIDIA Corporation
    Inventors: Ziyad Sami Hakura, Henry Packard Moreton, Emmett M. Kilgariff
  • Publication number: 20170132834
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Application
    Filed: January 20, 2017
    Publication date: May 11, 2017
    Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
  • Patent number: 9633469
    Abstract: A system, method, and computer program product are provided for conservative rasterization of primitives using an error term. In use, an edge equation is determined for each edge of a primitive, the edge equation having coefficients defining the edge of the primitive. Each edge of the primitive is shifted to enlarge the primitive by modifying coefficients of the edge equation defining the edge by an error term that is a predetermined amount. Pixels that intersect the primitive are then determined using the enlarged primitive.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 25, 2017
    Assignee: NVIDIA Corporation
    Inventors: Eric Brian Lum, Walter Robert Steiner, Henry Packard Moreton, Justin L. Cobb, Barry Nolan Rodgers, Yury Uralsky, Timo Oskari Aila, Tero Tapani Karras
  • Publication number: 20170046812
    Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.
    Type: Application
    Filed: October 24, 2016
    Publication date: February 16, 2017
    Inventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
  • Patent number: 9552667
    Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: January 24, 2017
    Assignee: NVIDIA Corporation
    Inventors: Yong He, Eric B. Lum, Eric Enderton, Henry Packard Moreton, Kayvon Fatahalian