Patents by Inventor Henry Packard Moreton
Henry Packard Moreton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9754561Abstract: One embodiment of the present invention includes a memory management unit (MMU) that is configured to manage sparse mappings. The MMU processes requests to translate virtual addresses to physical addresses based on page table entries (PTEs) that indicate a sparse status. If the MMU determines that the PTE does not include a mapping from a virtual address to a physical address, then the MMU responds to the request based on the sparse status. If the sparse status is active, then the MMU determines the physical address based on whether the type of the request is a write operation and, subsequently, generates an acknowledgement of the request. By contrast, if the sparse status is not active, then the MMU generates a page fault. Advantageously, the disclosed embodiments enable the computer system to manage sparse mappings without incurring the performance degradation associated with both page faults and conventional software-based sparse mapping management.Type: GrantFiled: October 4, 2013Date of Patent: September 5, 2017Assignee: NVIDIA CORPORATIONInventors: Jonathan Dunaisky, Henry Packard Moreton, Jeffrey A. Bolz, Yury Y. Uralsky, James Leroy Deming, Rui M. Bastos, Patrick R. Brown, Amanpreet Grewal, Christian Amsinck, Poornachandra Rao, Jerome F. Duluk, Jr., Andrew J. Tao
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Patent number: 9747661Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.Type: GrantFiled: October 24, 2016Date of Patent: August 29, 2017Assignee: NVIDIA CorporationInventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
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Patent number: 9747718Abstract: A system, method, and computer program product are provided for performing object-space shading. A primitive defined by vertices in three-dimensional (3D) space that is specific to an object defined by at least the primitive is received and a shading sample rate is computed for the primitive based on a screen-space derivative of coordinates of a pixel fragment transformed into the 3D space. A shader program is executed by a processing pipeline to compute shaded attributes for the primitive according to the computed shading sample rate.Type: GrantFiled: March 11, 2015Date of Patent: August 29, 2017Assignee: NVIDIA CorporationInventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, Jr., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
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Patent number: 9659399Abstract: A system, method, and computer program product are provided for passing attribute structures between shader stages of a processing pipeline. The method includes the steps of receiving data represented at a first level by a processing pipeline including an upstream shader unit, a downstream shader unit, and a processing unit. The upstream shader unit processes the data to generate a first set of attributes corresponding to the data represented at a second level. The upstream shader unit also stores the first set of the attributes in a first portion of a memory system that can be read by the downstream shader unit and any shader units that are downstream in the processing pipeline relative to the upstream shader unit. In one embodiment, the processing unit is coupled between the upstream shader unit and the downstream shader unit.Type: GrantFiled: August 23, 2013Date of Patent: May 23, 2017Assignee: NVIDIA CorporationInventors: Ziyad Sami Hakura, Henry Packard Moreton, Emmett M. Kilgariff
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Publication number: 20170132834Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.Type: ApplicationFiled: January 20, 2017Publication date: May 11, 2017Inventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
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Patent number: 9633469Abstract: A system, method, and computer program product are provided for conservative rasterization of primitives using an error term. In use, an edge equation is determined for each edge of a primitive, the edge equation having coefficients defining the edge of the primitive. Each edge of the primitive is shifted to enlarge the primitive by modifying coefficients of the edge equation defining the edge by an error term that is a predetermined amount. Pixels that intersect the primitive are then determined using the enlarged primitive.Type: GrantFiled: March 15, 2013Date of Patent: April 25, 2017Assignee: NVIDIA CorporationInventors: Eric Brian Lum, Walter Robert Steiner, Henry Packard Moreton, Justin L. Cobb, Barry Nolan Rodgers, Yury Uralsky, Timo Oskari Aila, Tero Tapani Karras
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Publication number: 20170046812Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.Type: ApplicationFiled: October 24, 2016Publication date: February 16, 2017Inventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
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Patent number: 9552667Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.Type: GrantFiled: December 13, 2013Date of Patent: January 24, 2017Assignee: NVIDIA CorporationInventors: Yong He, Eric B. Lum, Eric Enderton, Henry Packard Moreton, Kayvon Fatahalian
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Patent number: 9478066Abstract: A system, method, and computer program product are provided for adjusting vertex positions. One or more viewport dimensions are received and a snap spacing is determined based on the one or more viewport dimensions. The vertex positions are adjusted to a grid according to the snap spacing. The precision of the vertex adjustment may increase as at least one dimension of the viewport decreases. The precision of the vertex adjustment may decrease as at least one dimension of the viewport increases.Type: GrantFiled: March 14, 2013Date of Patent: October 25, 2016Assignee: NVIDIA CorporationInventors: Eric Brian Lum, Henry Packard Moreton, Kyle Perry Roden, Walter Robert Steiner, Ziyad Sami Hakura
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Patent number: 9418616Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.Type: GrantFiled: December 20, 2012Date of Patent: August 16, 2016Assignee: NVIDIA CORPORATIONInventors: Jerome F. Duluk, Jr., Ziyad S. Hakura, Henry Packard Moreton
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Patent number: 9355430Abstract: One embodiment sets forth a method for allocating memory to surfaces. A software application specifies surface data, including interleaving state data. Based on the interleaving state data, a surface access unit bloats addressees derived from discrete coordinates associated with the surface, creating a bloated virtual address space with a predictable pattern of addresses that do not correspond to data. Advantageously, by creating predictable regions of addresses that do not correspond to data, the software application program may configure the surface to share physical memory space with one or more other surfaces. In particular, the software application may map the virtual address space together with one or more virtual address spaces corresponding to complementary data patterns to the same physical base address. And, by overlapping the virtual address spaces onto the same pages in physical address space, the physical memory may be more densely packed than by using prior-art allocation techniques.Type: GrantFiled: September 20, 2013Date of Patent: May 31, 2016Assignee: NVIDIA CorporationInventors: Eric B. Lum, Cass W. Everitt, Henry Packard Moreton, Yury Y. Uralsky, Cyril Crassin, Jerome F. Duluk, Jr.
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Patent number: 9293109Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.Type: GrantFiled: December 20, 2012Date of Patent: March 22, 2016Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., Ziyad S. Hakura, Henry Packard Moreton
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Patent number: 9286659Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and is analyzed to identify subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample pixel data for all samples in the subset. An encoding state is generated that indicates which samples of the multi-sample pixel are included in each one of the subsets.Type: GrantFiled: March 15, 2013Date of Patent: March 15, 2016Assignee: NVIDIA CorporationInventors: Alexander Lev Minkin, Henry Packard Moreton, Yury Uralsky, Eric Brian Lum, Dale L. Kirkland, Steven James Heinrich, Rui Manuel Bastos, Emmett M. Kilgariff, Jeffrey Alan Bolz, Tyson Bergland, Patrick R. Brown
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Patent number: 9269179Abstract: A system, method, and computer program product are provided for generating primitive-specific attributes. In operation, it is determined whether a portion of a graphics processor is operating in a predetermined mode. If it is determined that the portion of the graphics processor is operating in the predetermined mode, only one or more primitive-specific attributes are generated in association with a primitive.Type: GrantFiled: March 15, 2013Date of Patent: February 23, 2016Assignee: NVIDIA CorporationInventors: Ziyad Sami Hakura, Yury Uralsky, Tyson Bergland, Dale L. Kirkland, Cyril Jean-Francois Crassin, Henry Packard Moreton
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Publication number: 20160049000Abstract: A system, method, and computer program product are provided for performing object-space shading. A primitive defined by vertices in three-dimensional (3D) space that is specific to an object defined by at least the primitive is received and a shading sample rate is computed for the primitive based on a screen-space derivative of coordinates of a pixel fragment transformed into the 3D space. A shader program is executed by a processing pipeline to compute shaded attributes for the primitive according to the computed shading sample rate.Type: ApplicationFiled: March 11, 2015Publication date: February 18, 2016Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, JR., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
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Publication number: 20160048999Abstract: A system, method, and computer program product are provided fir shading using a dynamic object-space grid. An object defined by triangle primitives in a three-dimensional (3D) space that is specific to the object is received and an object-space shading grid is defined for a first triangle primitive of the triangle primitives based on coordinates of the first triangle primitive in the 3D space. A shader program is executed by a processing pipeline to compute a shaded value at a point on the object-space shading grid for the first triangle primitive.Type: ApplicationFiled: March 11, 2015Publication date: February 18, 2016Inventors: Anjul Patney, Eric B. Enderton, Eric B. Lum, Marco Salvi, Christopher Ryan Wyman, Yubo Zhang, Yong He, G. Evan Hart, JR., Kayvon Fatahalian, Yury Uralsky, Henry Packard Moreton, Aaron Eliot Lefohn
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Patent number: 9262797Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.Type: GrantFiled: March 15, 2013Date of Patent: February 16, 2016Assignee: NVIDIA CorporationInventors: Alexander Lev Minkin, Henry Packard Moreton, Yury Uralsky, Eric Brian Lum, Dale L. Kirkland, Steven James Heinrich, Rui Manuel Bastos, Emmett M. Kilgariff, Jeffrey Alan Bolz, Tyson Bergland, Patrick R. Brown
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Patent number: 9165399Abstract: A system, method, and computer program product are provided for inputting modified coverage data into a pixel shader. In use, coverage data modified by a depth/stencil test is input into a pixel shader. Additionally, one or more actions are performed at the pixel shader, utilizing the modified coverage data.Type: GrantFiled: November 1, 2012Date of Patent: October 20, 2015Assignee: NVIDIA CorporationInventors: Yury Uralsky, Henry Packard Moreton
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Publication number: 20150170409Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: NVIDIA CORPORATIONInventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN
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Publication number: 20150170408Abstract: One embodiment of the present invention includes a parallel processing unit (PPU) that performs pixel shading at variable granularities. For effects that vary at a low frequency across a pixel block, a coarse shading unit performs the associated shading operations on a subset of the pixels in the pixel block. By contrast, for effects that vary at a high frequency across the pixel block, fine shading units perform the associated shading operations on each pixel in the pixel block. Because the PPU implements coarse shading units and fine shading units, the PPU may tune the shading rate per-effect based on the frequency of variation across each pixel group. By contrast, conventional PPUs typically compute all effects per-pixel, performing redundant shading operations for low frequency effects. Consequently, to produce similar image quality, the PPU consumes less power and increases the rendering frame rate compared to a conventional PPU.Type: ApplicationFiled: December 13, 2013Publication date: June 18, 2015Applicant: NVIDIA CORPORATIONInventors: Yong HE, Eric B. LUM, Eric ENDERTON, Henry Packard MORETON, Kayvon FATAHALIAN