Abstract: Implementations for a functional unit are provided, wherein the functional unit can accumulate more than two serial inputs and provide one serial summation output. The serial inputs and outputs can be single bits or multiple bit busses. The functional unit can be implemented as a logical tree, where any two points are connected by one path. The functional unit can be incorporated into a processing unit of a programmable device to allow for construction of various functions.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharding dataflow graphs for a device having multiple synchronous tiles. One of the methods includes receiving a representation of a dataflow graph comprising a plurality of nodes that each represent respective matrix operations to be performed by a device having a plurality synchronous tiles. Candidate allocations of respective portions of the dataflow graph to each tile of the plurality of synchronous tiles are evaluated according to one or more resource constraints of the device. One of the candidate allocations is selected based on evaluating each candidate allocation.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharding dataflow graphs for a device having multiple synchronous tiles. One of the methods includes receiving a representation of a dataflow graph comprising a plurality of nodes that each represent respective matrix operations to be performed by a device having a plurality synchronous tiles. Candidate allocations of respective portions of the dataflow graph to each tile of the plurality of synchronous tiles are evaluated according to one or more resource constraints of the device. One of the candidate allocations is selected based on evaluating each candidate allocation.

Abstract: The technology involves the auto-creation of custom standard cells. The process may include receiving specifications for implementing a set of functionalities in an integrated circuit to be fabricated. From this, the system identifies which cells are required to implement the set of functionalities. The identified cells are evaluated against a standard cell library stored in memory to determine which of the cells are not in the standard cell library. The system automatically creates the cells that are not in the standard cell library. The system can then utilize the automatically created cells to fabricate the integrated circuit. Benefits of such an approach include reduced design, development time and improved design quality of results. The resulting new cells may have fewer transistors, less area/power and improved performance than a standard cell from a preexisting library, especially since such standard cells would not necessarily be configurable to perform the desired functions.

Abstract: The technology involves transistor-level synthesis for integrated circuit design and fabrication. According to one aspect, a computer-implemented method performs transistor-level synthesis for an integrated circuit element. This includes generating single-stage transistor networks from Boolean functions, in which each single-stage transistor network is composed of a pulldown network and a pullup network. The single-stage transistor networks are scaled to multi-stage transistor networks to globally optimize for factored form literals. Technology mapping can then be performed based on the factored form literals to generate a circuit design.

Abstract: Implementations for a functional unit are provided, wherein the functional unit can accumulate more than two serial inputs and provide one serial summation output. The serial inputs and outputs can be single bits or multiple bit busses. The functional unit can be implemented as a logical tree, where any two points are connected by one path. The functional unit can be incorporated into a processing unit of a programmable device to allow for construction of various functions.

Abstract: A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for sharding dataflow graphs for a device having multiple synchronous tiles. One of the methods includes receiving a representation of a dataflow graph comprising a plurality of nodes that each represent respective matrix operations to be performed by a device having a plurality synchronous tiles. Candidate allocations of respective portions of the dataflow graph to each tile of the plurality of synchronous tiles are evaluated according to one or more resource constraints of the device. One of the candidate allocations is selected based on evaluating each candidate allocation.

Abstract: A programmable integrated circuit includes configuration circuitry configured to receive configurations of a user design for the programmable integrated circuit. Each of the configurations implements the user design using at least some unique circuitry in the programmable integrated circuit relative to the other ones of the configurations. The configuration circuitry is further configured to implement the user design in a first one of the configurations. The configuration circuitry is further configured to move the user design from the first one of the configurations to a second one of the configurations to cause effects of aging processes in circuits in the programmable integrated circuit that are not aged by the first one of the configurations.

Abstract: An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the user design, and configuration circuitry that couples the second circuits together through a network of conductors. Transistors in the second circuits turn on and off in response to a varying signal that propagates through the second circuits and through the network of conductors while the first circuits implement the user design.

Abstract: An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the user design, and configuration circuitry that couples the second circuits together through a network of conductors. Transistors in the second circuits turn on and off in response to a varying signal that propagates through the second circuits and through the network of conductors while the first circuits implement the user design.

Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

Abstract: In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.

Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.

Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.

Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.

Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.

Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.

Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.