Patents by Inventor Herman Schmit

Herman Schmit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190097635
    Abstract: An integrated circuit includes first circuits that are configured to implement a user design for the integrated circuit, second circuits that are unused by the user design, and configuration circuitry that couples the second circuits together through a network of conductors. Transistors in the second circuits turn on and off in response to a varying signal that propagates through the second circuits and through the network of conductors while the first circuits implement the user design.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 28, 2019
    Applicant: Intel Corporation
    Inventor: Herman Schmit
  • Publication number: 20180109262
    Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.
    Type: Application
    Filed: August 1, 2017
    Publication date: April 19, 2018
    Applicant: Altera Corporation
    Inventors: Andy Lee, Herman Schmit
  • Patent number: 9946826
    Abstract: In server virtualization, the resources of an integrated circuit are partitioned into smaller portions, and each of these smaller portions is then operated independently. Software is used to represent the smaller portions as virtual environments. For the purpose of server virtualization, an integrated circuit may include several different circuit designs, each implemented in a secure partition in the integrated circuit. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be verified as un-altered and from the respective user or owner and as having been approved by the integrated circuit owner and/or the circuit design implementation owner. The operation of the circuit design implementations in the integrated circuit may require that each circuit design implementation can be operated securely and independently of the other circuit design implementations in the integrated circuit.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: April 17, 2018
    Assignee: Altera Corporation
    Inventors: Sean Atsatt, Ting Lu, Dana How, Herman Schmit
  • Patent number: 9768783
    Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 19, 2017
    Assignee: Altera Corporation
    Inventors: Herman Schmit, Jiefan Zhang
  • Patent number: 9755647
    Abstract: An integrated circuit formed using a semiconductor substrate may include a logic circuit and a switch circuit, whereby the logic circuit operates at a first power supply voltage and the switch circuit operates at a second power supply voltage that is greater than the first power supply voltage. The logic circuit may be formed within a first triple well structure within the semiconductor substrate and is supplied with a first bias voltage. The switch circuit may be formed within a second triple well structure that is electrically isolated from the first triple well structure within the semiconductor substrate and is supplied with a second bias voltage. The switch circuit may receive a control signal that controls the first bias voltage and the second power supply voltage to turn off a transistor in the logic circuit during a programming operation of the integrated circuit.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: September 5, 2017
    Assignee: Altera Corporation
    Inventors: Andy Lee, Herman Schmit
  • Patent number: 9507900
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 29, 2016
    Assignee: Altera Corporation
    Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
  • Patent number: 9490814
    Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: November 8, 2016
    Assignee: Altera Corporation
    Inventors: Steven Teig, Herman Schmit, Randy Renfu Huang
  • Patent number: 9489175
    Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: November 8, 2016
    Assignee: Altera Corporation
    Inventors: Herman Schmit, Jason Redgrave
  • Patent number: 9385725
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: July 5, 2016
    Assignee: Altera Corporation
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
  • Patent number: 9385724
    Abstract: Integrated circuits such as application specific circuits or programmable logic devices may include specialized blocks such as configurable storage blocks and configurable processing blocks. Such specialized blocks may be controlled by clock signals and operated at single data rate or at double data rate. For instance, configurable storage blocks may be configured to use a double data rate communications scheme or a single data rate communication scheme to communicate data with other blocks. Configurable processing blocks may be configured to process data at a double data rate or a single data rate. Furthermore, configurable processing blocks that include accumulator circuitry may be configured to perform one accumulation at a single data rate or at a double data rate. Such configurable processing blocks may also be configured to perform two accumulations at a single data rate.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: July 5, 2016
    Assignee: Altera Corporation
    Inventors: Herman Schmit, Jiefan Zhang
  • Patent number: 9369363
    Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: June 14, 2016
    Assignee: Altera Corporation
    Inventor: Herman Schmit
  • Publication number: 20160087635
    Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.
    Type: Application
    Filed: March 28, 2015
    Publication date: March 24, 2016
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
  • Publication number: 20160028399
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.
    Type: Application
    Filed: March 20, 2015
    Publication date: January 28, 2016
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
  • Patent number: 9197531
    Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for a subset of the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using the word arrival times for the subset of words. Another embodiment relates to a method of determining an arrival time of a data packet which uses a measure of average fullness for a set of the FIFO buffers. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: November 24, 2015
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Herman Schmit
  • Patent number: 9165931
    Abstract: An integrated circuit (IC) includes a substrate that is common to the IC and variants of the IC. The IC also includes a first set of interconnect layers fabricated above the substrate. The first set of interconnect layers is used to couple programmable interconnect of the IC to a first circuit in the substrate. The IC further includes a second set of interconnect layers fabricated above the substrate. The second set of interconnect layers is used to differentiate features of the IC from variants of the IC by selectively coupling the programmable interconnect to a second circuit in the substrate.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: October 20, 2015
    Assignee: Altera Corporation
    Inventors: Herman Schmit, David Lewis, Michael D. Hutton, Dana How, Andy L. Lee
  • Publication number: 20150281031
    Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.
    Type: Application
    Filed: June 10, 2015
    Publication date: October 1, 2015
    Applicant: ALTERA CORPORATION
    Inventor: Herman SCHMIT
  • Patent number: 9118566
    Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using a predetermined function of the word arrival times. Another embodiment relates to a receiver circuit that determines an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: August 25, 2015
    Assignee: Altera Corporation
    Inventors: David W. Mendel, Herman Schmit
  • Patent number: 9083478
    Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.
    Type: Grant
    Filed: September 21, 2012
    Date of Patent: July 14, 2015
    Assignee: Altera Corporation
    Inventor: Herman Schmit
  • Patent number: 9041430
    Abstract: An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: May 26, 2015
    Assignee: TABULA, INC.
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
  • Publication number: 20150137851
    Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.
    Type: Application
    Filed: June 23, 2014
    Publication date: May 21, 2015
    Inventors: Herman Schmit, Jason Redgrave