Patents by Inventor Herman Schmit
Herman Schmit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150281031Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.Type: ApplicationFiled: June 10, 2015Publication date: October 1, 2015Applicant: ALTERA CORPORATIONInventor: Herman SCHMIT
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Patent number: 9118566Abstract: One embodiment relates to a method of determining an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Word arrival times for the words of the data packet are determined, each word arrival time corresponding to an arrival time of a word of the data packet at an individual lane of the multi-lane link. The arrival time of the data packet is determined using a predetermined function of the word arrival times. Another embodiment relates to a receiver circuit that determines an arrival time of a data packet which has data striped across a plurality of lanes of a multi-lane link. Other embodiments and features are also disclosed.Type: GrantFiled: February 11, 2013Date of Patent: August 25, 2015Assignee: Altera CorporationInventors: David W. Mendel, Herman Schmit
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Patent number: 9083478Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.Type: GrantFiled: September 21, 2012Date of Patent: July 14, 2015Assignee: Altera CorporationInventor: Herman Schmit
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Patent number: 9041430Abstract: An integrated circuit (IC) with a novel configurable routing fabric is provided. The configurable routing fabric has signal paths that propagate signals between user registers on user clock cycles. Each signal path includes a set of configurable storage elements and a set of configurable logic elements. Each configurable storage element in the path is reconfigurable on every sub-cycle of the user clock cycle to either store an incoming signal or to pass the incoming signal transparently.Type: GrantFiled: January 28, 2014Date of Patent: May 26, 2015Assignee: TABULA, INC.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Publication number: 20150137851Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.Type: ApplicationFiled: June 23, 2014Publication date: May 21, 2015Inventors: Herman Schmit, Jason Redgrave
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Publication number: 20150130508Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.Type: ApplicationFiled: July 14, 2014Publication date: May 14, 2015Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
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Patent number: 9018978Abstract: A novel configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations is provided. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. The configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. The configuration network is a pipelined network.Type: GrantFiled: April 25, 2014Date of Patent: April 28, 2015Assignee: Tabula, Inc.Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
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Patent number: 9018977Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.Type: GrantFiled: February 14, 2014Date of Patent: April 28, 2015Assignee: Tabula, Inc.Inventors: Jason Redgrave, Herman Schmit
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Publication number: 20150077158Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.Type: ApplicationFiled: April 7, 2014Publication date: March 19, 2015Applicant: Tabula, Inc.Inventors: Steven Teig, Herman Schmit, Randy Renfu Huang
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Publication number: 20150082261Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.Type: ApplicationFiled: April 7, 2014Publication date: March 19, 2015Applicant: Tabula, Inc.Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
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Publication number: 20140320165Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.Type: ApplicationFiled: April 25, 2014Publication date: October 30, 2014Applicant: Tabula, Inc.Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
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Publication number: 20140240001Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.Type: ApplicationFiled: January 28, 2014Publication date: August 28, 2014Applicant: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Patent number: 8810277Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.Type: GrantFiled: September 15, 2012Date of Patent: August 19, 2014Assignee: Tbula, Inc.Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
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Patent number: 8797062Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.Type: GrantFiled: July 16, 2012Date of Patent: August 5, 2014Assignee: Tabula, Inc.Inventors: Herman Schmit, Jason Redgrave
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Patent number: 8760194Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.Type: GrantFiled: October 25, 2011Date of Patent: June 24, 2014Assignee: Tabula, Inc.Inventors: Brad Hutchings, Jason Redgrave, Teju Khubehandani, Herman Schmit, Steven Teig
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Patent number: 8726213Abstract: Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of multiplexers that each has a set of input terminals, a set of output terminals, and a set of select terminals. The set of multiplexers includes a group of multiplexers, where at least one input terminal of each multiplexer in the group is a permanently inverting input terminal. During at least a set of cycles during the operation of the configurable IC, several multiplexers in the group of multiplexers are used to implement a particular function.Type: GrantFiled: March 30, 2009Date of Patent: May 13, 2014Assignee: Tabula, Inc.Inventors: Andrew Caldwell, Herman Schmit, Steven Teig
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Patent number: 8723549Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.Type: GrantFiled: December 5, 2011Date of Patent: May 13, 2014Assignee: Tabula, Inc.Inventors: Steven Teig, Herman Schmit, Randy Renfu Huang
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Publication number: 20140089720Abstract: One embodiment relates to a method for determining a latency of a network port. Read and write pointers for a FIFO are sampled at the same time. An average difference between a plurality of samples of the read and write pointers is determined. Another embodiment relates to an apparatus for providing timestamps to packets at a network port. Registers sample read and write pointers of a FIFO using a sampling clock. Logic circuitry determines an average difference between the read and write pointers, and timestamping circuitry receives the average difference and inserts timestamps into packets. Other embodiments and features are also disclosed.Type: ApplicationFiled: September 21, 2012Publication date: March 27, 2014Inventor: Herman SCHMIT
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Patent number: 8664974Abstract: A reconfigurable integrated circuit (“IC”) that has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time.Type: GrantFiled: January 21, 2011Date of Patent: March 4, 2014Assignee: Tabula, Inc.Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell
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Patent number: 8638119Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.Type: GrantFiled: May 21, 2012Date of Patent: January 28, 2014Assignee: Tabula, Inc.Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig