Patents by Inventor Herman Schmit

Herman Schmit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8436700
    Abstract: A MEMS-based switching device may be used to implement an interconnect switch in a programmable integrated circuit device. Such a MEMS-based device may include a deformable cantilever that may form a closed or open circuit to thereby implement switching functionality.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: May 7, 2013
    Assignee: eASIC Corporation
    Inventors: Herman Schmit, Sergey Gribok
  • Patent number: 8433891
    Abstract: Some embodiments of the invention provide a configuration/debug network for configuring and debugging a configurable integrated circuit (IC). The configurable IC in some embodiments includes configurable resources (e.g., configurable logic resources, routing resources, memory resources, etc.) that can be grouped in conceptual configurable tiles that are arranged in several rows and columns. Some embodiments allow tiles to be individually addressed, globally addressed (i.e., all addressed together), or addressed based on their tile types. The configurable IC includes numerous user-design state elements (“UDS elements”) in some embodiments. In some embodiments, the configuration/debug network has a streaming mode that can direct various circuits in one or more configurable tiles to stream out their data during the operation of the configurable IC.
    Type: Grant
    Filed: August 27, 2010
    Date of Patent: April 30, 2013
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Brad Hutchings, Steven Teig, Herman Schmit, Teju Khubchandani
  • Patent number: 8434045
    Abstract: Some embodiments provide a method of providing configurable ICs to a user. The method provides the configurable IC and a set of behavioral descriptions to the user. The behavioral descriptions specify the effects of accesses to a memory by a set of memory ports given a set of parameters chosen by the user.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: April 30, 2013
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Daniel J. Pugh, Steven Teig
  • Publication number: 20130099819
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.
    Type: Application
    Filed: September 15, 2012
    Publication date: April 25, 2013
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Publication number: 20130038347
    Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.
    Type: Application
    Filed: July 16, 2012
    Publication date: February 14, 2013
    Inventors: Herman Schmit, Jason Redgrave
  • Publication number: 20130031316
    Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 31, 2013
    Inventors: Herman Schmit, Steven Teig, Brad Hutchings
  • Publication number: 20130021057
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.
    Type: Application
    Filed: May 21, 2012
    Publication date: January 24, 2013
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Patent number: 8339844
    Abstract: A semiconductor device may be created using multiple metal layers and a layer including programmable vias that may be used to form various patterns of interconnections among segments of metal layers. The programmable vias may be formed of materials whose resistance is changeable between a high-resistance state and a low-resistance state.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: December 25, 2012
    Assignee: eASIC Corporation
    Inventors: Herman Schmit, Ronnie Vasishta, Adam Levinthal, Jonathan Park
  • Patent number: 8305110
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: November 6, 2012
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Patent number: 8248102
    Abstract: Some embodiments provide a configurable IC that includes several configurable logic circuits, where the logic circuits include several sets of associated configurable logic circuits. For each several sets of associated configurable logic circuits, the reconfigurable IC also includes a carry circuit for performing up to N carry operations sequentially, wherein N is greater than two.
    Type: Grant
    Filed: May 17, 2010
    Date of Patent: August 21, 2012
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Herman Schmit, Steven Teig, Brad L. Hutchings, Randy R. Huang
  • Patent number: 8230182
    Abstract: Some embodiments provide for a method of mapping a user design to a configurable integrated circuit (IC). The method is for a configurable IC that implements a user design with an associated user design clock cycle. The IC operates on a sub-cycle clock that has multiple sub-cycle periods within a user period of the user design clock cycle. The method identifies multiple port accesses to a first multi-port memory defined in the user design. The accesses are in a single user design clock cycle. The method maps the multiple port accesses to the first multi-port memory to multiple physical-port memory accesses to a second physical-port memory in the configurable IC during multiple sub-cycles associated with a single user design clock cycle.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: July 24, 2012
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Steven Teig, Brad Hutchings
  • Publication number: 20120139579
    Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 7, 2012
    Inventors: Steven Teig, Herman Schmit, Randy Renfu Huang
  • Patent number: 8193830
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes a logic circuit for receiving input data sets and configuration data sets and performing several functions on the input data sets. Each configuration data set specifies a particular function that the logic circuit has to perform on the input data set. The IC also includes a connection circuit for supplying sets of the configuration data to the logic circuit at a particular rate for at least a particular time period. At least two supplied configuration data sets are different and configure the logic circuit to perform two different functions on the input data.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: June 5, 2012
    Assignee: Tabula, Inc.
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Patent number: 8183882
    Abstract: Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: May 22, 2012
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Herman Schmit, Jason Redgrave
  • Publication number: 20120098567
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 26, 2012
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubehandani, Herman Schmit, Steven Teig
  • Patent number: 8115510
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that includes several configurable circuits grouped in several tiles. The configurable IC also includes a configuration network for loading configuration data into the IC, where the configuration data is for configuring several of the configurable circuit. In some embodiments, the configuration network includes several registers at several boundaries between the tiles, where the registers allow multiple configuration data sets to be routed to multiple tiles concurrently. The configuration network in some embodiments includes several address counters at several tiles, where each address counter allows one address to be loaded for a tile and then to be successively incremented based on increment instructions sent over the configuration network. At least, two different addresses specified by an address counter of a particular tile identify two different resources within the particular tile.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: February 14, 2012
    Assignee: Tabula, Inc.
    Inventors: Jason Redgrave, Teju Khubchandani, Herman Schmit
  • Patent number: 8093922
    Abstract: Some embodiments provide a configurable IC that includes a configurable routing fabric with storage elements. In some embodiments, the routing fabric provides a communication pathway that routes signals to and from source and destination components. The routing fabric of some embodiments provides the ability to selectively store the signals passing through the routing fabric within the storage elements of the routing fabric. In this manner, a source or destination component continually performs operations (e.g., computational or routing) irrespective of whether a previous signal from or to such a component is stored within the routing fabric. The source and destination components include configurable logic circuits, configurable interconnect circuits, and various other circuits that receive or distribute signals throughout the configurable IC.
    Type: Grant
    Filed: April 6, 2009
    Date of Patent: January 10, 2012
    Assignee: Tabula, Inc.
    Inventors: Steven Teig, Herman Schmit, Randy Renfu Huang
  • Patent number: 8067960
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC) that has several configurable circuits for configurably performing different operations. During the operation of the IC, each particular configurable circuit performs a particular operation that is specified by a particular configuration data set for the particular configurable circuit. While the IC operates and a first set of configurable circuits performs a first set of operations, configuration data is loaded from the outside of the IC for configuring a second set of configurable circuits. In some embodiments, the configurable IC includes a configuration network for rapid loading configuration data in the IC from outside of the IC. In some of these embodiments, the configuration network is a pipelined network.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: November 29, 2011
    Assignee: Tabula, Inc.
    Inventors: Brad Hutchings, Jason Redgrave, Teju Khubchandani, Herman Schmit, Steven Teig
  • Publication number: 20110267102
    Abstract: Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.
    Type: Application
    Filed: April 8, 2011
    Publication date: November 3, 2011
    Inventors: Herman Schmit, Michael Butts, Brad L. Hutchings, Steven Teig
  • Publication number: 20110181317
    Abstract: Some embodiments provide a reconfigurable integrated circuit (“IC”). This IC has several reconfigurable circuits, each having several configurations for several configuration cycles. The reconfigurable circuits include several time-extending reconfigurable circuits. During the operation of the IC, each particular time-extending reconfigurable circuit maintains at least one of its configurations over at least two contiguous cycles, in order to allow a signal to propagate through a signal path, which contains the particular time-extending circuit, within a desired amount of time. Some embodiments provide a method of designing a reconfigurable IC that has several reconfigurable circuits, each having several configurations and operating in several reconfiguration cycles. The method identifies a signal path through the IC that does not meet a timing constraint. The signal path includes several circuits, one of which is a particular reconfigurable circuit.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Inventors: Andre Rohe, Steven Teig, Herman Schmit, Jason Redgrave, Andrew Caldwell