Abstract: A connector is described for fixing a plurality of switching assemblies on a substrate. The connector is also for making contact with the plurality of switching assemblies, which have compatible interfaces. The connector has a plurality of receptacle devices with contact elements and internal contact connections between corresponding contact elements, as a result of which, the length of the connections between the switching assemblies is reduced, signal propagation times are shortened and a higher clock rate for operating the switching assemblies is made possible.

Abstract: A zero insertion force mount for fixing and making contact with circuit subassemblies on a substrate has a plurality of holding devices for holding the circuit subassemblies and a zero insertion force device (ZIF mechanism), in a stressed state of the zero insertion force device. The circuit subassemblies are disposed in the holding devices being fixed by a pressing force exerted via the contact elements.

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

Abstract: Memory modules without signal-conditioning devices (unbuffered, unregistered) are provided in a system by using adapter cards that have signal-conditioning devices and are then operated in the manner of memory modules with signal-conditioning devices (buffered, registered). Systems can thereby be expanded in a very simple manner and can be flexibly adapted according to requirements, and for this purpose only one type (unbuffered, unregistered) of memory module is required.

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

Abstract: In order to be able to ensure the signal integrity in the simplest possible manner, both in the event of reading and in the event of writing, in the case of changing and rising transmission rates when a control device accesses at least one semiconductor circuit module, it is proposed that a termination impedance device that is provided for impedance matching with regard to the access by the control device to the semiconductor circuit modules provided is configured to be switchable between a plurality of impedance states.

Abstract: In a configuration for data transmission in a semiconductor memory system, in which data are transmitted between at least one semiconductor memory module and a memory controller controlled by a system clock signal, additional sense clock signal lines are led between the memory controller and the memory modules and, via loops on the memory modules, are led back directly from the memory modules to the memory controller component. By transmitting a sense clock signal from the memory controller to each of the memory modules via the additional sense clock signal lines, the memory controller is able to measure the respective signal propagation time of the sense clock signal and adjust a delay time for the data signals respectively received from the memory modules appropriately. The use of a data strobe signal and the associated disadvantages when testing the memory system or the memory modules is rendered superfluous.

Abstract: A memory device comprises a memory module, a controller, a data bus, means for providing a read clock and a read clock bus. Means for providing a read clock is arranged in the memory module, so that the data bus and the read clock bus are substantially symmetric.

Abstract: The invention relates to an electronic assembly having a non-volatile memory device with a controllable write protection feature and a switching configuration for generating a write protection signal from potentials at the supply terminals of the electronic assembly.

Abstract: An integrated circuit has connecting pads for outputting digital signals, a connection for a time reference signal, and an assessment circuit to measure and assess a phase shift between one of the digital signals and the time reference signal. A receiver circuit is connected to a respective junction between one of the connecting pads and an associated output driver. A device for matching propagation times of signals applied to the receiver circuit is provided. The assessment circuit is connected to the receiver circuit and has an output to output a measured result. In each case, the phase shift of the signals to be output in relation to the time reference signal is measured and assessed separately. An offset of the switching edges of the signals to be output can be determined relatively accurately and corrected.

Abstract: An internal clock signal of a logic/memory component that receives signals is transmitted as a reference clock to a transmitting logic/memory component. With the aid of the reference clock, the transmission clock of the output unit of the transmitting logic/memory component is generated, such that transmitted signals arrive in a receiving unit of the receiving component synchronously with the internal clock signal of that component.

Abstract: The invention relates to a method and to an input circuit for evaluating a data item in a data signal at an input of a memory component. The data signal is integrated between a start time and an end time that are specified by a control signal. An integration period between the start time and the end time depends on the frequency of the data signal. The data item is assigned a logic data value based on the result of the integration. The input circuit has a comparator device, an integration device and a switching device. The data signal is first integrated in order to obtain an integration value. The comparator device compares the integration value with a prescribed threshold value. A logic data value is assigned to the data item based on the result of the comparison.

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

Abstract: The invention relates to an evaluation device for assessing a digital data signal having a sampling device, a processing unit and a data memory. The sampling device is configured to sample the data signal multiply in a temporally offset manner within a predetermined time period and to store the samples of the data signal in the data memory. The processing unit is configured to output a data value of the data signal in a manner dependent on the samples at an output of the evaluation device.

Abstract: The invention relates to a system and to a method for repairing bit errors in memory chips having a multiplicity of memory cells, in which a bit error is detected using an error identification algorithm, the address of the faulty memory cell is determined and the fault is repaired by activating a redundant memory cell, with the repair being effected in the memory chip's finally installed state with the end user.

Abstract: An apparatus includes at least one dynamic random access memory (DRAM) array; and at least one temperature sensor in thermal communication with the DRAM array and operable to produce a signal indicative of a temperature of the DRAM array.

Abstract: A sense amplifier configuration includes a semiconductor substrate, a well having a variable well potential and insulated in the semiconductor substrate, and at least one field-effect transistor in the well. The transistor has a short channel length and an adjustable threshold voltage. Locating the field-effect transistor in an insulated well with a controllable potential allows for compensation of deviations in the threshold voltage with the substrate control effect. The threshold voltage can increase with increasingly larger negative voltage values of the well potential. The threshold voltage has an actual value and a target value, and the well potential can be controlled as a function of a difference between the actual and target threshold voltage values. The well potential can vary from approximately +200 mV to −400 mV, and in steps of approximately 50 mV.