Abstract: The invention relates to a semiconductor memory module having a plurality of memory chips arranged next to one another in a row. The memory module has a module-internal clock, command/address and data bus which transfers clock signal, command and address signals and also data signals from a memory controller device to the memory chips and data signals from the memory chips to the memory controller device. The memory module has respective clock, command/address and data signal lines. The clock signal lines comprise two differential clock signal lines which, at their end opposite to the memory controller device are either open or connected to one another by a short-circuiting bridge. The memory chips, during a write operation, synchronize the write data with the clock signal running from the memory controller device to the end of the clock signal line and, during a read operation, output the read data synchronously with the clock signal reflected from the open or short-circuited end of the clock signal lines.

Abstract: Method for repairing hardware faults in memory chips. According to one embodiment, a method is provided for repairing bit errors in memory chips having a multiplicity of memory cells. The method can include detecting bit errors using an error identification algorithm. Further, the method can include determining the addresses of faulty memory cells. The method can also include setting a data bit initiating a repair mode in response to detecting a bit error. In the repair mode, a signal present on a data line to the memory chips can be interpreted as a repair command to perform a repair. In addition, the method can include repairing the bit errors by activating redundant memory cells.

Abstract: A multi-chip package and method is disclosed. In one embodiment, the multi-chip package includes at least four of spaced semiconductor integrated circuit chips mounted on a printed circuit board, consisting of the first pair of the semiconductor integrated circuit chips and the second pair of the semiconductor integrated circuit chips. The chips of the first pair of the semiconductor integrated circuit chips are arranged substantially parallel and the chips of the semiconductor integrated circuit chips of the second pair are arranged substantially stacked over the chips of the first pair of the semiconductor integrated circuit chips.

Abstract: An apparatus for storing memory words with a plurality of memory element stacks is described, wherein the memory element stacks have a plurality of memory elements of ascending ranking order, and wherein a memory element of higher ranking order can be accessed via one or a plurality of memory elements of lower ranking order, wherein the apparatus for storing memory words further has a means for distributed storage of a memory word on the plurality of memory element stacks, wherein a memory word is stored in at least two memory element stacks in memory elements of different ranking order.

Abstract: A semiconductor memory system is disclosed. In one embodiment, the semiconductor memory system and memory module of the present invention provides a buffer, wherein at least one write buffer chip on the memory module is only buffering and registering write data, command and address signals written from a memory controller to the memory chips. As read data are written back from each memory chip directly to the memory controller through unidirectional point-to-point read data lines the present semiconductor memory system achieves a low latency as compared with a fully buffered DIMM concept. As read data are only unidirectional a high transmission bandwidth can be achieved.

Abstract: In a semiconductor memory system, the memory chips are linked to a memory module in a shared loop forward architecture and connected in a point-to-point connection to a memory controller. Each memory chip includes a high-speed interface circuit including: a read and write data/command-and-address signal re-driver/transmitter path for re-driving serial read data and write data/command-and-address signals not destined for the semiconductor memory chip; and a main signal path which includes a serial-to-parallel converter and a synchronizer for serial-to-parallel converting and synchronizing with a reference clock signal write data/command-and-address signals destined for the semiconductor memory chip as well as a parallel-to-serial converter for parallel-to-serial converting read data signals read from a memory core of the memory chips, and a switch for inserting the parallel-to-serial converted read data signals into the re-driver/transmitter path.

Abstract: A semiconductor memory chip includes a re-drive unit for re-driving electrical signals to at least one semiconductor memory chip connected thereto. The re-drive unit includes a direct line connection between two connecting nodes, i.e., one input terminal and one output terminal of the semiconductor memory chip.

Abstract: A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, serial signal line bus for control and address signals connected with the memory controller, directly connecting at least one semiconductor memory chip with the memory controller and serially connecting with each other the semiconductor memory chips among each other by 1-point-to-1-point connections.

Abstract: A semiconductor memory arrangement for operation in a data memory system with at least one semiconductor memory chip for the storage of user data includes a memory controller for control of the at least one semiconductor memory chip, and at least one unidirectional signal line bus for control and address signals connected with the memory controller and branching at least once. The at least once branching bus directly connecting at least one semiconductor memory chip with the memory controller and connecting the semiconductor memory chips among each other.

Abstract: One embodiment of the present invention provides to a memory device adapted to receive data according to a write clock signal and to output data according to a read clock signal, comprising a clock port configured to output the read clock signal and to receive the write clock signal and a serial bidirectional driver configured to output the read clock signal via the clock port and to receive the write clock signal via the clock port simultaneously.

Abstract: A semiconductor memory device including semiconductor memory cells with at least one memory cell capable of either acting as a storage device for ECC information or of acting as a redundant memory cell is provided. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either as a storage device or as a redundant memory cell. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either as a storing device for ECC information or as a redundant memory cell.

Abstract: A semiconductor memory device includes semiconductor memory cells with at least one memory cell capable of acting either in a first mode, wherein it functions as a storage device for ECC information, or in a second mode, wherein it functions as either as a redundant memory cell or a as a cell storing ordinary information. The semiconductor memory device further includes a signal control device for signaling if the at least one memory cell is to be used either in the first mode or in the second mode. A method of operating a semiconductor memory device is also provided including the steps of registering a status of a signal device and, depending on the status of the signal device, operating the at least one memory cell either in the first mode or in either of the selected second modes.

Abstract: The invention describes a semiconductor memory module unit for P2P data interchange with a memory controller. Memory chips having different data widths can be arranged on the semiconductor memory module unit in such a way as to enable a tree-like branching by signal data transmission from a node-like memory chip to a plurality of downstream memory chips while retaining the data width.

Abstract: The present invention relates to a memory system having a memory device with two clock lines. One embodiment of the present invention provides a memory system comprising at least one memory device, a memory controller to control operation of the memory device, a first clock line which extends from a write clock output of the memory controller to a clock port of the memory device to provide a clock signal to the memory device, and a second clock line which extends from the clock port of the memory device to a read clock input of the memory controller to forward the clock signal applied to the clock port of the memory device back to a read clock input of the memory controller. The memory device may further comprise a synchronization circuit adapted to receive the clock signal from the memory controller and to, provide an output data synchronized to the forwarded clock signal.

Abstract: The present invention includes a semiconductor memory modules and semiconductor memory systems using the same. The modules divide a conventional DIMM into a series of separate, smaller memory modules. Each memory module includes at least one semiconductor memory chip arranged on a substrate; CAwD signal input lines arranged on the substrate in a first predetermined line number and connecting one of the semiconductor memory chips to CAwD input signal pins on the substrate; and rD signal output lines arranged on the substrate in a second predetermined line number and connecting the one or a last semiconductor memory to a second number of rD output signal pins of the substrate. In a semiconductor memory system including the semiconductor memory modules, each memory module is separately connected to a memory controller by the CAwD signal input linesand the rD signal output lines in a respective point-to-point fashion.

Abstract: A method for operating a semiconductor memory device system, and a semiconductor memory device system are disclosed. In one embodiment, the system includes a memory device and a control means connected with the memory device via a bus system, wherein a single signal line or a single signal line pair of the bus system is provided for the transmission of a status signal that signalizes that control data are to be transmitted from the memory device to the control means, or from the control means to the memory device.

Abstract: A memory device includes at least two DRAM memory modules, at least one external ECC module, and a memory controller. The external ECC module provides the memory modules with ECC functionality. Each memory module is connected to the memory controller via a respective memory channel. The external ECC modules are connected to the memory controller via a common ECC channel. Each external ECC module is assigned to a group of the memory modules. The memory modules of one group with respective ECC modules are synchronously operated by the memory controller.

Abstract: A memory system and method is disclosed. In one embodiment, the memory system includes a memory controller and at least one memory module on which a certain number of semiconductor memory chips and connecting lines are arranged in a respectively specified topology. The connecting lines include first connecting lines forming transfer channels for a protocol based transfer of data and command signal streams from the memory controller to at least one of the memory chips on the memory module and from there to the memory controller, respectively. Second connecting lines are routed separately from the memory controller directly to at least one of the memory chips on the memory module for transferring select information to the at least one memory chip separately from the data and command signal streams.

Abstract: A method for setting an address of a rank in a memory module having a number of memory chips distributed along a byte lane includes setting the first memory chip of the byte lane to have a first rank address, generating a second rank address therein from the first rank address, and driving the second rank address to a second one of the memory chips. Alternatively, the first rank address may be driven to the second memory chip, and then, a second rank address is generated in that second memory chip. Further, the second memory chip is set to have the second rank address in response to the driving the second/first rank address. A power-up sequence after voltage supply, or command signals sent via a serial management bus or the command address bus can be used to initiate the setting of ranks. The rank addresses are re-driven to adjacent memory chips by DQ-lines along a byte lane.

Abstract: A circuit system includes a means for controlling a first and a second memory unit by means of a differential control signal. The differential control signal includes a first control signal and a second control signal, which is inverted to the first control signal. Further, the circuit system comprises a differential control signal line, which includes a first signal line for routing the first control signal and a second signal line for routing the second control signal. The first switching unit is connected via the first signal line and the second circuit unit is connected via the second signal line to the means for controlling.