Patents by Inventor Hideaki Kuwabara

Hideaki Kuwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9786687
    Abstract: [Summary] [Problem] A TFT is manufactured using at least five photomasks in a conventional liquid crystal display device, and therefore the manufacturing cost is high. [Solving Means] By performing the formation of the pixel electrode 127, the source region 123 and the drain region 124 by using three photomasks in three photolithography steps, a liquid crystal display device prepared with a pixel TFT portion, having a reverse stagger type n-channel TFT, and a storage capacitor can be realized.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideaki Kuwabara, Yasuyuki Arai
  • Patent number: 9786689
    Abstract: An object is to provide a semiconductor device having a structure with which parasitic capacitance between wirings can be sufficiently reduced. An oxide insulating layer serving as a channel protective layer is formed over part of an oxide semiconductor layer overlapping with a gate electrode layer. In the same step as formation of the oxide insulating layer, an oxide insulating layer covering a peripheral portion of the oxide semiconductor layer is formed. The oxide insulating layer which covers the peripheral portion of the oxide semiconductor layer is provided to increase the distance between the gate electrode layer and a wiring layer formed above or in the periphery of the gate electrode layer, whereby parasitic capacitance is reduced.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 10, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiroki Ohara, Toshinari Sasaki, Kosei Noda, Hideaki Kuwabara
  • Publication number: 20170278878
    Abstract: A technique is described in which a transistor formed using an oxide semiconductor film, a transistor formed using a polysilicon film, a transistor formed using an amorphous silicon film or the like, a transistor formed using an organic semiconductor film, a light-emitting element, or a passive element is separated from a glass substrate by light or heat. An oxide layer is formed over a light-transmitting substrate, a metal layer is selectively formed over the oxide layer, a resin layer is formed over the metal layer, an element layer is formed over the resin layer, a flexible film is fixed to the element layer, the resin layer and the metal layer are irradiated with light through the light-transmitting substrate, the light-transmitting substrate is separated, and a bottom surface of the metal layer is made bare.
    Type: Application
    Filed: March 20, 2017
    Publication date: September 28, 2017
    Inventors: Hideaki KUWABARA, Hiroki ADACHI, Satoru IDOJIRI
  • Patent number: 9766526
    Abstract: A method of manufacturing, with high mass productivity, liquid crystal display devices having highly reliable thin film transistors with excellent electric characteristics is provided. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: September 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Hideaki Kuwabara, Hajime Kimura
  • Publication number: 20170263777
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
    Type: Application
    Filed: May 31, 2017
    Publication date: September 14, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA
  • Patent number: 9741779
    Abstract: One object is to provide a semiconductor device with a structure which enables reduction in parasitic capacitance sufficiently between wirings. In a bottom-gate type thin film transistor including a stacked layer of a first layer which is a metal thin film oxidized partly or entirely and an oxide semiconductor layer, the following oxide insulating layers are formed together: an oxide insulating layer serving as a channel protective layer which is over and in contact with a part of the oxide semiconductor layer overlapping with a gate electrode layer; and an oxide insulating layer which covers a peripheral portion and a side surface of the stacked oxide semiconductor layer.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 22, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara, Hideaki Kuwabara
  • Publication number: 20170223442
    Abstract: Headphones including a sound output unit, a processing unit, a memory unit, a lighting unit, and a detection unit are provided. The sound output unit is configured to output sound. The memory unit is configured to store a program. The lighting unit is configured to emit light in response to a signal supplied from the processing unit. The detection unit is configured to obtain detection information and supply a detection signal corresponding to the detection information to the processing unit. The processing unit is configured to read out the program, carry out an operation using the detection signal and the program, and supply a signal corresponding to an operation result to the lighting unit.
    Type: Application
    Filed: January 26, 2017
    Publication date: August 3, 2017
    Inventors: Hideaki KUWABARA, Natsuko TAKASE
  • Patent number: 9722054
    Abstract: An object is, in a thin film transistor in which an oxide semiconductor is used as an active layer, to prevent change in composition, film quality, an interface, or the like of an oxide semiconductor region serving as an active layer, and to stabilize electrical characteristics of the thin film transistor. In a thin film transistor in which a first oxide semiconductor region is used as an active layer, a second oxide semiconductor region having lower electrical conductivity than the first oxide semiconductor region is formed between the first oxide semiconductor region and a protective insulating layer for the thin film transistor, whereby the second oxide semiconductor region serves as a protective layer for the first oxide semiconductor region; thus, change in composition or deterioration in film quality of the first oxide semiconductor region can be prevented, and electrical characteristics of the thin film transistor can be stabilized.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kengo Akimoto, Toshinari Sasaki, Hideaki Kuwabara
  • Patent number: 9698368
    Abstract: A FET is formed on a semiconductor substrate, a curved surface having a radius of curvature is formed on an upper end of an insulation, a portion of a first electrode is exposed corresponding to the curved surface to form an inclined surface, and a region defining a luminescent region is subjected to etching to expose the first electrode. Luminescence emitted from an organic chemical compound layer is reflected by the inclined surface of the first electrode to increase a total quantity of luminescence taken out in a certain direction.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: July 4, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Hideaki Kuwabara
  • Publication number: 20170168575
    Abstract: An input device having flexibility includes a display portion, a touch panel, a haptic element, a haptic controller, and a control portion. The touch panel is configured to acquire information on the size of a user's body part operating the input device and transmit the information to the control portion. The control portion is configured to receive the information, generate information on the positioning of a plurality of buttons, and transmit the information to the display portion. The display portion is configured to display the plurality of buttons on the basis of the received information. The haptic controller is configured to transmit information on a haptic effect to the haptic element.
    Type: Application
    Filed: December 1, 2016
    Publication date: June 15, 2017
    Inventors: Takahiro KASAHARA, Hideaki KUWABARA
  • Patent number: 9673337
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit included in an LSI, a CPU, or a memory is manufactured using the transistor which is formed using an oxide semiconductor which is an intrinsic or substantially intrinsic semiconductor obtained by removal of impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than a silicon semiconductor, and is formed over a semiconductor substrate. With the transistor which is formed over the semiconductor substrate and includes the highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device whose power consumption due to leakage current is low can be realized.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: June 6, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Patent number: 9666601
    Abstract: In a display device such as a liquid crystal display device, a large sized display screen is realized under low power consumption. A surface of a source wiring line of a pixel portion employed in an active matrix type liquid crystal display device is processed by way of a plating process operation so as to lower a resistance value of this source wiring line. The source wiring line of the pixel portion is manufactured at a step different from a step for manufacturing a source wiring line of a drive circuit portion. Further, electrodes of a terminal portion are processed by a plating process operation so as to reduce a resistance value thereof.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hideaki Kuwabara, Saishi Fujikawa
  • Patent number: 9666689
    Abstract: An object is to reduce the number of photomasks used for manufacturing a transistor and manufacturing a display device to less than the conventional one. The display device is manufactured through, in total, three photolithography steps including one photolithography step which serves as both a step of forming a gate electrode and a step of forming an island-like semiconductor layer, one photolithography step of forming a contact hole after a planarization insulating layer is formed, and one photolithography step which serves as both a step of forming a source electrode and a drain electrode and a step of forming a pixel electrode.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hideaki Kuwabara
  • Patent number: 9666678
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel formation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 30, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hiroyuki Miyake, Kei Takahashi, Kouhei Toyotaka, Masashi Tsubuku, Kosei Noda, Hideaki Kuwabara
  • Publication number: 20170148827
    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.
    Type: Application
    Filed: February 8, 2017
    Publication date: May 25, 2017
    Inventors: Masayuki SAKAKURA, Hideto OHNUMA, Hideaki KUWABARA
  • Patent number: 9653519
    Abstract: A light emitting device having a high definition, a high aperture ratio and a high reliability is provided. The present invention realizes a high definition and a high aperture ratio for a flat panel display of full colors using luminescent colors of red, green and blue without being dependent upon the film formation method and deposition precision of an organic compound layer by forming the laminated sections 21, 22 by means of intentionally and partially overlapping different organic compound layers of adjacent light emitting elements. Moreover, the protective film 32a containing hydrogen is formed and the drawback in the organic compound layer is terminated with hydrogen, thereby realizing the enhancement of the brightness and the reliability.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: May 16, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaaki Hiroki, Masakazu Murakami, Hideaki Kuwabara
  • Publication number: 20170125454
    Abstract: To provide a semiconductor device in which a layer to be peeled is attached to a base having a curved surface, and a method of manufacturing the same, and more particularly, a display having a curved surface, and more specifically a light-emitting device having a light emitting element attached to a base with a curved surface. A layer to be peeled, which contains a light emitting element furnished to a substrate using a laminate of a first material layer which is a metallic layer or nitride layer, and a second material layer which is an oxide layer, is transferred onto a film, and then the film and the layer to be peeled are curved, to thereby produce a display having a curved surface.
    Type: Application
    Filed: November 10, 2016
    Publication date: May 4, 2017
    Inventors: Toru TAKAYAMA, Junya MARUYAMA, Yuugo GOTO, Hideaki KUWABARA, Shunpei YAMAZAKI
  • Publication number: 20170110692
    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.
    Type: Application
    Filed: December 28, 2016
    Publication date: April 20, 2017
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Kuwabara, Hideto Ohnuma
  • Patent number: 9627459
    Abstract: To provide a light emitting device high in reliability with a pixel portion having high definition with a large screen. According to a light emitting device of the present invention, on an insulator (24) provided between pixel electrodes, an auxiliary electrode (21) made of a metal film is formed, whereby a conductive layer (20) made of a transparent conductive film in contact with the auxiliary electrode can be made low in resistance and thin. Also, the auxiliary electrode (21) is used to achieve connection with an electrode on a lower layer, whereby the electrode can be led out with the transparent conductive film formed on an EL layer. Further, a protective film (32) made of a film containing hydrogen and a silicon nitride film which are laminated is formed, whereby high reliability can be achieved.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: April 18, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masaaki Hiroki, Masakazu Murakami, Hideaki Kuwabara
  • Publication number: 20170092776
    Abstract: An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory. A semiconductor integrated circuit such as an LSI, a CPU, or a memory is manufactured using a thin film transistor in which a channel fog nation region is formed using an oxide semiconductor which becomes an intrinsic or substantially intrinsic semiconductor by removing impurities which serve as electron donors (donors) from the oxide semiconductor and has larger energy gap than that of a silicon semiconductor. With use of a thin film transistor using a highly purified oxide semiconductor layer with sufficiently reduced hydrogen concentration, a semiconductor device with low power consumption due to leakage current can be realized.
    Type: Application
    Filed: December 8, 2016
    Publication date: March 30, 2017
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Hiroyuki MIYAKE, Kei TAKAHASHI, Kouhei TOYOTAKA, Masashi TSUBUKU, Kosei NODA, Hideaki KUWABARA