Patents by Inventor Hideaki Sakaguchi
Hideaki Sakaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20120229157Abstract: In one embodiment, a probe card is provided. The probe card includes: a substrate having a first surface and a second surface opposite to the first surface; a through hole formed through the substrate and extending between the first surface and the second surface; an elastic member formed in the through hole to extend to the first surface; a through electrode formed in through hole to extend to the second surface; a first trace on a surface of the elastic member to be electrically connected to the through electrode; and a contact bump on the elastic member via the first trace to be electrically connected to the first trace, wherein the contact bump is electrically connected to an electrode pad formed on a DUT (device under test) when an electrical testing is performed on the DUT using the probe card.Type: ApplicationFiled: February 23, 2012Publication date: September 13, 2012Applicant: Shinko Electric Industries Co., Ltd.Inventors: Akinori SHIRAISHI, Hideaki SAKAGUCHI, Mitsutoshi HIGASHI
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Patent number: 8227909Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.Type: GrantFiled: December 16, 2010Date of Patent: July 24, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Mitsutoshi Higashi, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama
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Patent number: 8183679Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: GrantFiled: July 14, 2011Date of Patent: May 22, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 8137497Abstract: A method includes the steps of providing a first tape base material on a single side of a stiffener substrate, forming, on the stiffener substrate, a cavity for accommodating a semiconductor chip therein, inserting the stiffener substrate in the cavity and providing the stiffener substrate on the first tape base material, sealing the semiconductor chip and the stiffener substrate with a sealing resin, and removing the first tape base material and forming a build-up layer on a tape removing surface.Type: GrantFiled: March 24, 2009Date of Patent: March 20, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
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Publication number: 20120049876Abstract: [Problems to be solved] To provide a test-use individual substrate capable of improving testing accuracy and connecting reliability. [Means for solving the Problems] A test-use individual substrate 30 which is used for testing a semiconductor wafer, comprises a main body portion 31, thin portions 321, 322 extending from the main body portion 31 and being relatively thinner than the main body portion, and bumps 33 provided on the thin portions 321, 322. [Selected Drawing] FIG.Type: ApplicationFiled: August 18, 2011Publication date: March 1, 2012Applicants: SHINKO ELECTRIC INDUSTRIES CO., LTD., ADVANTEST CORPORATIONInventors: Shigeru MATSUMURA, Kohei KATO, Katsushi SUGAI, Koichi SHIROYAMA, Mitsutoshi HIGASHI, Akinori SHIRAISHI, Hideaki SAKAGUCHI
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Patent number: 8108993Abstract: A method of manufacturing a wiring substrate is disclosed. The method includes: (a) preparing a supporting substrate including a main body and a through electrode penetrating the main body, wherein the supporting substrate includes a first surface and a second surface opposite to the first surface, and a trace is formed on the second surface of the supporting substrate; (b) forming a build-up wiring structure by alternately forming a wiring layer and an insulating layer on the first surface of the supporting substrate; and (c) obtaining a wiring substrate by separating the build-up wiring structure from the supporting substrate. Step (b) includes: forming the wiring layer using the through electrode as a power feeding wiring, and step (c) includes: peeling the build-up wiring structure from the supporting substrate to obtain the wiring substrate.Type: GrantFiled: March 13, 2009Date of Patent: February 7, 2012Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsutoshi Higashi, Kei Murayama, Masahiro Sunohara, Hideaki Sakaguchi
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Patent number: 8080122Abstract: There are provided a step of preparing a dummy chip, a step of forming a cavity in a stiffener substrate, a step of providing a second tape base member on one surface of the stiffener substrate, a step of inserting the dummy chip into the cavity to provide the dummy chip on the second tape base member, a step of sealing the stiffener substrate and the dummy chip with a sealing resin, a step of removing the second tape base member and forming a build-up wiring layer on a surface from which the second tape base member is removed, a step of removing the sealing resin; and a step of peeling the dummy chip from the build-up wiring layer.Type: GrantFiled: March 24, 2009Date of Patent: December 20, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Masahiro Sunohara, Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi
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Patent number: 8053886Abstract: A semiconductor package includes a wiring board and a semiconductor device mounted on the wiring board. At least one penetration hole extends from one surface of the semiconductor chip to an opposite surface of the semiconductor chip. A penetration electrode is situated inside the penetration hole without contacting a wall of the penetration hole. The penetration electrode has one end fixed to the one surface of the semiconductor chip and an opposite end protruding from the opposite surface of the semiconductor chip. A connection terminal is formed on the opposite end of the penetration electrode and electrically connected to the wiring board.Type: GrantFiled: August 5, 2009Date of Patent: November 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuichi Taguchi, Mitsutoshi Higashi, Akinori Shiraishi, Hideaki Sakaguchi, Masahiro Sunohara
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Publication number: 20110266697Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: ApplicationFiled: July 14, 2011Publication date: November 3, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hideaki SAKAGUCHI, Masahiro Sunohara, Mitsutoshi Higashi
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Publication number: 20110260744Abstract: A probe card for conducting an electrical test on a test subject includes a substrate body including a first surface, which faces toward the test subject, and a second surface, which is opposite to the first surface. A through electrode extends through the substrate body between the first surface and the second surface. A contact bump is formed in correspondence with the electrode pad and electrically connected to the through electrode. An elastic body is filled in an accommodating portion, which is formed in the substrate body extending from the first surface toward the second surface. The contact bump is formed on the elastic body.Type: ApplicationFiled: April 19, 2011Publication date: October 27, 2011Applicant: Shinko Electric Industries Co., LTD.Inventors: Akinori Shiraishi, Hideaki Sakaguchi, Mitsutoshi Higashi
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Patent number: 8044429Abstract: A light-emitting device including a light-emitting element and a substrate where the light-emitting element is arranged. A housing part housing the light-emitting element and having a shape that is tapered upward from the substrate and a metal frame surrounding the light-emitting element and including the side face of the housing part made into an almost mirror-polished surface are provided on the substrate.Type: GrantFiled: October 19, 2010Date of Patent: October 25, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Mitsutoshi Higashi, Masahiro Sunohara, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama, Naoyuki Koizumi, Hideaki Sakaguchi
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Publication number: 20110256662Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: ApplicationFiled: June 23, 2011Publication date: October 20, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
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Patent number: 8008120Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: GrantFiled: December 28, 2010Date of Patent: August 30, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7989707Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: GrantFiled: December 12, 2006Date of Patent: August 2, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Patent number: 7981798Abstract: The present disclosure relates to a method of manufacturing a substrate. The method includes: (a) forming through holes by applying an anisotropic etching to a silicon substrate from a first surface of the silicon substrate; (b) forming a first insulating film to cover the first surface of the silicon substrate, surfaces of the silicon substrate exposed from the through holes, and a second surface of the silicon substrate opposite to the first surface; (c) forming an opening in a portion of the first insulating film provided on the second surface, the portion of the first insulating film corresponding to an area in which the through holes are formed; (d) etching the silicon substrate using the first insulating film provided on the second surface as a mask, thereby forming a cavity in the silicon substrate; and (e) removing the first insulating film.Type: GrantFiled: September 19, 2008Date of Patent: July 19, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Yuichi Taguchi, Akinori Shiraishi, Masahiro Sunohara, Kei Murayama, Hideaki Sakaguchi, Mitsutoshi Higashi
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Publication number: 20110156242Abstract: There is provided a method of manufacturing a semiconductor package. The method includes: (a) providing a silicon wafer comprising a first surface and a second surface opposite to the first surface; (b) forming vias through the silicon wafer in its thickness direction; (c) forming wiring patterns on the first surface of the silicon wafer such that the wiring patterns are electrically connected to the vias; (d) bonding a MEMS element wafer comprising MEMS elements onto the second surface of the silicon wafer such that the MEMS elements are electrically connected to the vias; (e) dividing the MEMS element wafer into the respective MEMS elements; (f) bonding a lid having concave portions therein onto the second surface of the silicon wafer such that the respective MEMS elements face a corresponding one of the concave portions; and (g) dicing the lid and the silicon wafer.Type: ApplicationFiled: December 16, 2010Publication date: June 30, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hideaki Sakaguchi, Mitsutoshi Higashi, Yuichi Taguchi, Akinori Shiraishi, Kei Murayama
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Publication number: 20110147951Abstract: A wiring substrate includes a wiring layer, an insulating layer formed on the wiring layer, a connection pad formed on the insulating layer, and a via conductor formed to penetrate the insulating layer, and connecting the wiring layer and the connection pad, wherein the wiring layer located under the connection pad is formed to have via receiving electrode portion whose area is smaller than an area of the connection pad, and a wiring portion separated from the via receiving electrode portion, in an area corresponding to the connection pad, and the via receiving electrode portion is connected to the connection pad via the via conductor.Type: ApplicationFiled: December 2, 2010Publication date: June 23, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Kei MURAYAMA, Masahiro Sunohara, Akinori Shiraishi, Hideaki Sakaguchi
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Publication number: 20110092020Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: ApplicationFiled: December 28, 2010Publication date: April 21, 2011Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Hideaki SAKAGUCHI, Masahiro Sunohara, Mitsutoshi Higashi
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Patent number: 7900807Abstract: In a conductive ball mounting apparatus for mounting one conductive ball on each of a plurality of pads which are provided on a substrate and on which an adhesive is formed, the conductive ball mounting apparatus includes: a conductive ball container for containing a plurality of conductive balls therein and having an opening to pass through the plurality of conductive balls; a substrate holder disposed over the conductive ball container to face the opening, and holding the substrate in such a manner that the plurality of conductive balls and the plurality of pads face each other and the substrate is disposed over the conductive ball container with a space therebetween; and a conductive ball supplying unit for supplying the plurality of conductive balls to the plurality of pads via the opening by moving up the plurality of conductive balls.Type: GrantFiled: March 9, 2010Date of Patent: March 8, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kiyoaki Iida, Kazuo Tanaka, Norio Kondo, Hideaki Sakaguchi, Mitsutoshi Higashi
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Patent number: 7897432Abstract: A peeling off layer 18 is formed on an entire surface of one surface side of a support plate 10 including the inner wall surfaces respectively of a recessed part 12 for an electronic part and recessed parts 16 for posts in which the posts 20 are formed. Then, the recessed parts 16 are filled with metal to form the posts 20. Then, conductor patterns 28 are formed that electrically connect the electrode terminals 22a of the electronic part 22 inserted into the recessed part 12 to the posts 20. Then, an insulating layer covering the conductor patterns 28 is formed to form an electronic part package 30 on the one surface side of the support plate 10 through the peeling off layer 18. After that, the electronic part package 30 is separated from the support plate 10 by the peeling off layer 18.Type: GrantFiled: September 4, 2009Date of Patent: March 1, 2011Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hideaki Sakaguchi, Masahiro Sunohara, Mitsutoshi Higashi