Patents by Inventor Hideaki Yamauchi

Hideaki Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8366421
    Abstract: A fluid pressure pulsation damper mechanism includes: a metal damper having two metal diaphragms joined together with a hermetic seal for forming a sealed spacing filled with a gas between the two metal diaphragms, an edge part overlapping along outer peripheries thereof, a main body having a damper housing in which the metal damper is accommodated, and a cover attached to the main body to cover the damper housing and isolate the damper housing from outside air.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: February 5, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Akihiro Munakata, Hideki Machimura, Hideaki Yamauchi, Daisuke Kitajima, Masashi Nemoto
  • Patent number: 8339830
    Abstract: According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Yamauchi, Daichi Kaku, Takehiko Hojo
  • Publication number: 20120320062
    Abstract: A figure drawing device includes; a device 2 for increasing/decreasing the number of pixels on a scanning line up to the final painting pixel by one pixel; a device 3 for increasing/decreasing the number of scanning lines for drawing by one line; a device 4 for outputting drawing pixel data based on the control by the devices 1 and 2; a stencil buffer 5 for holding figure data in an intermediate stage of sequentially drawing a figure; a device 6 for holding pixel data read from the buffer 5 and consecutive as plural pieces of pixel data; a device 7 for detecting the transit state of the data value in the device 6; and a device 8 for inverting/non-inverting the logical operation result of the output data of the device 4 and the data in the device 6 and writing a result to the buffer 5.
    Type: Application
    Filed: July 13, 2012
    Publication date: December 20, 2012
    Inventor: Hideaki YAMAUCHI
  • Publication number: 20120243357
    Abstract: According to one embodiment, a memory cell is configured using a field effect transistor and includes n anti-fuse elements, one ends of which are connected in common. A program voltage selection circuit selects, out of the n anti-fuse elements, an anti-fuse element to which a program voltage is applied. A sense amplifier is provided for the each memory cell and determines, based on data stored in the n anti-fuse elements, three or more values of readout levels.
    Type: Application
    Filed: September 15, 2011
    Publication date: September 27, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki Yamauchi, Daichi Kaku, Takehiko Hojo
  • Patent number: 8270179
    Abstract: In a case where the first component and the third component are mountable on the first circuit board pattern of the first individual board and the second component is mountable on the second circuit board pattern of the first individual board, or in a case where the first component is mountable on the first circuit board pattern of the second individual board, and the second component and the third component are mountable on the second circuit board pattern of the second individual board, in the first and second individual boards, traces for the third component are provided so that electrical connections between the third component and the other components are identical between the case where the third component is mounted on the first circuit board pattern, and the case where the third component is mounted on the second circuit board pattern.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: September 18, 2012
    Assignee: Panasonic Corporation
    Inventors: Hideaki Yamauchi, Haruya Sakuma, Masataka Saitoh
  • Publication number: 20120200217
    Abstract: A method of production of a radio frequency accelerator which has a tubular part 1 which forms an acceleration cavity, including a temporary assembly step of making a plurality of component members 11 to 14 which have shapes obtained by splitting the tubular part 1 mate with each other to temporarily assemble them into the shape of the tubular part 10 and a welding step of welding the plurality of component members 11 to 14 together. The temporary assembly step includes a step of placing, inside of the tubular part 1, support members 21 for contacting the inside surface of the tubular part 1 and supporting the tubular part 1 from the inside, and the welding step includes a step of welding the plurality of component members 11 to 14 along the butt lines 51 by friction stir welding.
    Type: Application
    Filed: October 14, 2010
    Publication date: August 9, 2012
    Applicants: TOKYO INSTITUTE OF TECHNOLOGY, TIM CORPORATION, INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
    Inventors: Noriyosu Hayashizaki, Toshiyuki Hattori, Takuya Ishibashi, Fujio Naito, Eiichi Takasaki, Hideaki Yamauchi
  • Publication number: 20120199103
    Abstract: In a conventional high-pressure fuel pump, the interference fit part between a plunger and a retainer comes loose with time due to environmental factors and this reduces the clearance between the retainer and a tappet more than necessity, resulting in increase in the contact face pressure between the plunger and a cylinder when a side force acts on the plunger, which causes seizure between the plunger and the cylinder. In this invention, a protrusion protruding toward the tappet is provided around the through-hole for press-fitting the plunger, the through-hole provided in the center portion of the retainer. Since the clearance between the retainer and the tappet can sufficiently be kept even if the joint between the retainer and the plunger comes loose, the seizure between the plunger and the cylinder and the breakage of the plunger are less likely to occur even if the side force acts on the retainer.
    Type: Application
    Filed: August 17, 2010
    Publication date: August 9, 2012
    Applicant: Hitachi Automotive Systems Ltd
    Inventors: Minoru Hashida, Hiroyuki Yamada, Masayuki Suganami, Sunao Takahashi, Toru Onose, Hideaki Yamauchi, Kazuichi Ishige
  • Patent number: 8120620
    Abstract: A graphics system including: a register storing data of a clipping frame of a frame buffer; a register storing offset data of a figure; a register storing data of a clipping frame of a stencil buffer that is larger than the clipping frame of the frame buffer and storing position data of a reference basing point, on a stencil buffer, for drawing a non-offset figure or an offset figure; and a pixel filling-in module for drawing onto a stencil buffer a masking determination result of a pixel relating to the figure on the basis of data of the clipping frame of the stencil buffer and the figure, and also drawing the non-offset figure or the offset figure onto the frame buffer by referring to the stencil buffer onto which the masking determination result is drawn, the position data of a reference basing point stored in the register, and the data of the clipping frame of the frame buffer.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: February 21, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hideaki Yamauchi
  • Patent number: 7916145
    Abstract: The challenge of the present invention is to prevent a crook line part of a dotted line from being displayed in half tone. The present invention is contrived to calculate a center coordinate of a texture pixel in a zone including a reference texture beginning point coordinate S_Begin as reference texture corrected beginning point coordinate S_Begin?. It is followed by calculating a center coordinate of a texture pixel in a zone including a reference texture end coordinate S_End as reference texture corrected end coordinate S_End?. A crook line part of a dotted line is drawn by fixing a reference coordinate to the S_Begin? or S_End? if a pixel to be drawn exists within a fixing section.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 29, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hideaki Yamauchi
  • Patent number: 7859531
    Abstract: A graphic apparatus that draws an object three-dimensionally using a level plane and a height-axis perpendicular to the level plane includes a receiving unit, a calculating unit, and a drawing unit. The receiving unit receives vertex data identifying a position of a top surface of the object on the level plane. The calculating unit calculates a modulation coefficient of luminance for the top surface based on a normal vector for the top surface and a light-source vector indicating a direction of a light source on the level plane. The drawing unit draws the top surface using the vertex data and the modulation coefficient, and a top surface of another object using the modulation coefficient.
    Type: Grant
    Filed: May 29, 2008
    Date of Patent: December 28, 2010
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hideaki Yamauchi
  • Patent number: 7796397
    Abstract: Provided is an electronic components assembly capable of effectively dealing with unwanted charge accumulated in a capacitor even when general-purpose components are used. An assembly 10 includes an electrolytic capacitor 1, a coil lead 4, and a circuit mounting board 5. The electrolytic capacitor 1 includes a main body 1a, an anode lead 2, and a cathode lead 3. The coil lead 4 is wrapped around the main body 1a. The circuit mounting board 5 has the electrolytic capacitor 1 and the coil lead 4 mounted thereon. The coil lead 4 is connected to a ground of the circuit mounting board 5.
    Type: Grant
    Filed: August 22, 2007
    Date of Patent: September 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Hideaki Yamauchi, Masayuki Asai, Shuusaku Yamamoto, Takashi Sakaguchi, Takashi Yamamoto
  • Publication number: 20100226193
    Abstract: A unit memory circuit includes a fuse element capable of electrically programming data. A sense amplifier circuit is connected to the fuse element. The sense amplifier circuit senses data of the fuse element. Either of a first interconnect and a second interconnect is selectively formed by changing an interconnect formation mask. The first interconnect is short-circuiting the fuse element and the second interconnect is cutting off a current path when data is read from the fuse element.
    Type: Application
    Filed: December 8, 2009
    Publication date: September 9, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki Yamauchi, Hiroaki Nakano
  • Publication number: 20100157559
    Abstract: In a case where the first component and the third component are mountable on the first circuit board pattern of the first individual board and the second component is mountable on the second circuit board pattern of the first individual board, or in a case where the first component is mountable on the first circuit board pattern of the second individual board, and the second component and the third component are mountable on the second circuit board pattern of the second individual board, in the first and second individual boards, traces for the third component are provided so that electrical connections between the third component and the other components are identical between the case where the third component is mounted on the first circuit board pattern, and the case where the third component is mounted on the second circuit board pattern.
    Type: Application
    Filed: December 22, 2009
    Publication date: June 24, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: HIDEAKI YAMAUCHI, HARUYA SAKUMA, MASATAKA SAITOH
  • Publication number: 20100002003
    Abstract: A figure drawing device includes; a device 2 for increasing/decreasing the number of pixels on a scanning line up to the final painting pixel by one pixel; a device 3 for increasing/decreasing the number of scanning lines for drawing by one line; a device 4 for outputting drawing pixel data based on the control by the devices 1 and 2; a stencil buffer 5 for holding figure data in an intermediate stage of sequentially drawing a figure; a device 6 for holding pixel data read from the buffer 5 and consecutive as plural pieces of pixel data; a device 7 for detecting the transit state of the data value in the device 6; and a device 8 for inverting/non-inverting the logical operation result of the output data of the device 4 and the data in the device 6 and writing a result to the buffer 5.
    Type: Application
    Filed: September 10, 2009
    Publication date: January 7, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hideaki YAMAUCHI
  • Publication number: 20090303240
    Abstract: A graphics system including: a register storing data of a clipping frame of a frame buffer; a register storing offset data of a figure; a register storing data of a clipping frame of a stencil buffer that is larger than the clipping frame of the frame buffer and storing position data of a reference basing point, on a stencil buffer, for drawing a non-offset figure or an offset figure; and a pixel filling-in module for drawing onto a stencil buffer a masking determination result of a pixel relating to the figure on the basis of data of the clipping frame of the stencil buffer and the figure, and also drawing the non-offset figure or the offset figure onto the frame buffer by referring to the stencil buffer onto which the masking determination result is drawn, the position data of a reference basing point stored in the register, and the data of the clipping frame of the frame buffer.
    Type: Application
    Filed: June 15, 2009
    Publication date: December 10, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hideaki YAMAUCHI
  • Publication number: 20090073180
    Abstract: A graphics drawing apparatus drawing a graphic, including: a generation unit, where a sequence of two-dimensional coordinates of vertices is input, generating the coordinates of each of the vertices and virtual vertex coordinates for the coordinates of each of the vertices on a memory, the virtual vertex coordinates being generated by converting the X-coordinate value of the coordinates of each of the vertices to the X-coordinate value of the coordinates of the leading vertex of the sequence; and a setting unit that sets the coordinates of two vertices of a partial graphic that is to be created as the coordinates of two adjacent vertices, in sequence starting from the leading vertex, and, after setting the coordinates of the trailing vertex of the sequence, setting the coordinates of two vertices of the partial graphic that is to be created as the coordinates of the leading and trailing vertices.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 19, 2009
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Hideaki YAMAUCHI
  • Publication number: 20080289713
    Abstract: A fluid pressure pulsation damper mechanism comprising: a metal damper having two metal diaphragms joined together with a hermetic seal for forming a sealed spacing filled with a gas between the two metal diaphragms, an edge part at which are overlapped along outer peripheries thereof; a main body having a damper housing in which the metal damper is accommodated; and a cover attached to the main body to cover the damper housing and isolate the damper housing from an outside air, the metal damper being held between the cover and the main body; wherein the cover is further comprising: a metal plate for making the cover, a peripheral edge of the cover being joined to the main body, a plurality of inner convex curved parts extending toward the main body and a plurality of outer convex curved parts extending in a direction away from the main body, and a plurality of the inner convex curved parts and a plurality of the outer convex parts being disposed alternately inside the peripheral edge of the cover at which th
    Type: Application
    Filed: May 20, 2008
    Publication date: November 27, 2008
    Applicant: Hitachi, Ltd.
    Inventors: Akihiro Munakata, Hideki Machimura, Hideaki Yamauchi, Daisuke Kitajima, Masashi Nemoto
  • Publication number: 20080284494
    Abstract: A fuse device includes a plurality of serially connected fuse elements whose number is n (n is an integer of two or more), a power source connected to one end of a first fuse element that is a top of the n serially connected fuse elements, and a plurality of program control transistors. Each of the program control transistors is connected to each of nodes between the fuse elements, and to an end of the n-th fuse element, respectively.
    Type: Application
    Filed: May 9, 2008
    Publication date: November 20, 2008
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hideaki Yamauchi, Akikuni Sato, Takehiko Hojo
  • Publication number: 20080225051
    Abstract: A graphic apparatus that draws an object three-dimensionally using a level plane and a height-axis perpendicular to the level plane includes a receiving unit, a calculating unit, and a drawing unit. The receiving unit receives vertex data identifying a position of a top surface of the object on the level plane. The calculating unit calculates a modulation coefficient of luminance for the top surface based on a normal vector for the top surface and a light-source vector indicating a direction of a light source on the level plane. The drawing unit draws the top surface using the vertex data and the modulation coefficient, and a top surface of another object using the modulation coefficient.
    Type: Application
    Filed: May 29, 2008
    Publication date: September 18, 2008
    Applicant: FUJITSU LIMITED
    Inventor: Hideaki YAMAUCHI
  • Publication number: 20080049408
    Abstract: Provided is an electronic components assembly capable of effectively dealing with unwanted charge accumulated in a capacitor even when general-purpose components are used. An assembly 10 includes an electrolytic capacitor 1, a coil lead 4, and a circuit mounting board 5. The electrolytic capacitor 1 includes a main body 1a, an anode lead 2, and a cathode lead 3. The coil lead 4 is wrapped around the main body 1a. The circuit mounting board 5 has the electrolytic capacitor 1 and the coil lead 4 mounted thereon. The coil lead 4 is connected to a ground of the circuit mounting board 5.
    Type: Application
    Filed: August 22, 2007
    Publication date: February 28, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hideaki YAMAUCHI, Masayuki ASAI, Shuusaku YAMAMOTO, Takashi SAKAGUCHI, Takashi YAMAMOTO