Abstract: The challenge of the present invention is to prevent a crook line part of a dotted line from being displayed in half tone. The present invention is contrived to calculate a center coordinate of a texture pixel in a zone including a reference texture beginning point coordinate S_Begin as reference texture corrected beginning point coordinate S_Begin?. It is followed by calculating a center coordinate of a texture pixel in a zone including a reference texture end coordinate S_End as reference texture corrected end coordinate S_End?. A crook line part of a dotted line is drawn by fixing a reference coordinate to the S_Begin? or S_End? if a pixel to be drawn exists within a fixing section.

Abstract: A graphic system includes a texture storage area 4b for storing a broken line texture image in which broken line patterns by modifier function are arranged, a texture module 3b for reading a specific broken line pattern arranged in the broken line texture image based on coordinates on the broken line texture image, a drawing module 3c for drawing a broken line using the broken line pattern read by the texture module 3b.

Abstract: An image processing apparatus and graphics memory unit which reduces useless memory access to a graphics memory unit. When an image data read section reads image data from frame buffers or windows, a mask area inside/outside determination section determines by reference to mask information stored in a mask information storage section whether image data which is being scanned is in a memory access mask area. If the image data which is being scanned is in the memory access mask area, then a superposition process section performs a superposition process according to a transmission attribute assigned to the memory access mask area regardless of transmission attributes assigned to the frame buffers or the windows.

Abstract: In a bird's eye view or the like, performance degrades due to a too high vertex density, and as a result, beauty is ruined. In order to solve such problems, an amount of features is calculated based on the relative position of the previously drawn vertex and a closely located vertex to it. Then, if the amount of features meets a specific threshold condition, the relevant vertex is eliminated from drawing targets, and a vertex the amount of features of which does not meet the threshold condition is specified as a subsequent drawing target.

Abstract: A semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an arrangement that avoids areas overlapping positions of the wires.

Abstract: A modem coupling circuit comprising: (a) a transformer 1 having a core 1a including a gap formed therein, primary windings N1a, N1b constituting a bifilar wound coil which is wound around the core 1a, forming a single layer and connected to power lines L1, L2, and a secondary winding N2 connected to a transmitting circuit 2 and a secondary winding N3 connected to a receiving circuit 3, the secondary windings N2, N3 holding the single layer of the primary windings between; (b) a coupling capacitor C1 connected to a middle point between first ends of the primary windings, the first ends being not connected to the power lines L1, L2; (c) current limiting resistances R1a, R1b connected to the primary windings N1a, N1b having a bifilar construction; (d) drive resistances R2a, R2b connected to the secondary winding for transmission N2; and (e) terminating resistances R3a, R3b connected to the secondary winding for reception N3.

Abstract: The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.

Abstract: A modem coupling circuit comprising: (a) a transformer 1 having a core 1a including a gap formed therein, primary windings N1a, N1b constituting a bifilar wound coil which is wound around the core 1a, forming a single layer and connected to power lines L1, L2, and a secondary winding N2 connected to a transmitting circuit 2 and a secondary winding N3 connected to a receiving circuit 3, the secondary windings N2, N3 holding the single layer of the primary windings between; (b) a coupling capacitor C1 connected to a middle point between first ends of the primary windings, the first ends being not connected to the power lines L1, L2; (c) current limiting resistances R1a, R1b connected to the primary windings N1a, N1b having a bifilar construction; (d) drive resistances R2a, R2b connected to the secondary winding for transmission N2; and (e) terminating resistances R3a, R3b connected to the secondary winding for reception N3.

Abstract: A semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an arrangement that avoids areas overlapping positions of the wires.

Abstract: A semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an arrangement that avoids areas overlapping positions of the wires.

Abstract: A seal mechanism with improved pressure tightness is provided to eliminate a return piping to a fuel tank used for reducing pressure applied to the seal mechanism in a high pressure fuel pump. The seal mechanism includes a stress reduction mechanism for reducing the stress generated at the junction between its retaining member and flexible member.

Abstract: The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.

Abstract: A semiconductor device includes a real pattern and dummy patterns in respective different coordinate systems. Using a dummy pattern in a single coordinate system does not allow an effective dummy pattern arrangement. To the contrary, if the dummy patterns in different coordinate systems are used, minimum interval requirements may be satisfied in one coordinate system while such requirements are not met in another coordinate system.

Abstract: The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14, 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22, 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.

Abstract: The semiconductor device comprises a semiconductor substrate 10; a capacitor element 40 formed above the semiconductor substrate and including a lower electrode 34, a capacitor insulation film 36 formed on the lower electrode and an upper electrode 38 formed on the capacitor insulation film; a shield layer 14; 58 formed at least either of above and below the capacitor element; and a lead-out interconnection layer 22; 50 formed between the capacitor element and the shield layer and electrically connected to the lower electrode or the upper electrode, a plurality of holes 16, 60 being formed in each of the shield layer and the lead-out interconnection layer. The shield layers are formed above and below the MIM capacitor, whereby combination of noises with the MIM capacitor can be prevented.

Abstract: A seal mechanism with improved pressure tightness is provided to eliminate a return piping to a fuel tank used for reducing pressure applied to the seal mechanism in a high pressure fuel pump. The seal mechanism includes a stress reduction mechanism for reducing the stress generated at the junction between its retaining member and flexible member.

Abstract: A semiconductor device having a ferroelectric capacitor is formed by the steps of forming a lower electrode on a substrate, applying a rapid thermal annealing process to the lower electrode, depositing, after the step of rapid thermal annealing process, a ferroelectric film on the lower electrode, crystallizing the ferroelectric film by applying a thermal annealing process to the ferroelectric film, and forming an upper electrode on the ferroelectric insulation film.

Abstract: A semiconductor device includes a real pattern and dummy patterns in respective different coordinate systems. Using a dummy pattern in a single coordinate system does not allow an effective dummy pattern arrangement. To the contrary, if the dummy patterns in different coordinate systems are used, minimum interval requirements may be satisfied in one coordinate system while such requirements are not met in another coordinate system.

Abstract: A semiconductor integrated circuit includes a plurality of layers provided on a semiconductor substrate, wires provided in a first layer that is one of the plurality of layers, and wire dummies provided in a second layer different from the first layer and having an arrangement that avoids areas overlapping positions of the wires.

Abstract: A vehicle navigation system performs regular travel guidance with respect to a guidance target intersection at a specific distance short of the intersection. When a distance between first and second guidance target intersections is shorter than the specific distance, regular travel guidance with respect to the second guidance target intersection is not performed. In this case, the vehicle navigation system performs supplementary travel guidance with respect to the second guidance target intersection immediately after passing through the first guidance target intersection. Accordingly, travel guidance can always be performed with respect to an immediate guidance target intersection.