Patents by Inventor Hidefumi Takaya

Hidefumi Takaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120161154
    Abstract: An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.
    Type: Application
    Filed: December 20, 2011
    Publication date: June 28, 2012
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Tomohiro MIMURA, Shinichiro MIYAHARA, Hidefumi TAKAYA, Masahiro SUGIMOTO, Narumasa SOEJIMA, Tsuyoshi ISHIKAWA, Yukihiko WATANABE
  • Publication number: 20120142173
    Abstract: A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.
    Type: Application
    Filed: December 1, 2011
    Publication date: June 7, 2012
    Applicant: DENSO CORPORATION
    Inventors: Hiroki WATANABE, Yasuo KITOU, Yasushi FURUKAWA, Kensaku YAMAMOTO, Hidefumi TAKAYA, Masahiro SUGIMOTO, Yukihiko WATANABE, Narumasa SOEJIMA, Tsuyoshi ISHIKAWA
  • Publication number: 20120068296
    Abstract: Provided is a semiconductor device capable of reducing a temperature-dependent variation of a current sense ratio and accurately detecting current In the semiconductor device, at least one of an impurity concentration and a thickness of each semiconductor layer is adjusted such that a value calculated by a following equation is less than a predetermined value: [ ? i = 1 n ? ( R Mi × k Mi ) - ? i = 1 n ? ( R Si × k Si ) ] / ? i = 1 n ? ( R Mi × k Mi ) where a temperature-dependent resistance changing rate of an i-th semiconductor layer (i=1 to n) of the main element domain is RMi; a resistance ratio of the i-th semiconductor layer of the main element domain relative to the entire main element domain is kMi; a temperature-dependent resistance changing rate of the i-th semiconductor layer of the sense element domain is RSi; and a resistance ratio of the i-th semiconductor layer of the sense element domain to the entire sense element domain is kSi.
    Type: Application
    Filed: May 29, 2009
    Publication date: March 22, 2012
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Kimimori Hamada, Yuji Nishibe
  • Publication number: 20120061682
    Abstract: A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 15, 2012
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Toshimasa Yamamoto, Masahiro Sugimoto, Hidefumi Takaya, Jun Morimoto, Narumasa Soejima, Tsuyoshi Ishikawa, Yukihiko Watanabe
  • Publication number: 20120012860
    Abstract: A SiC semiconductor device includes a reverse type MOSFET having: a substrate; a drift layer and a base region on the substrate; a base contact layer and a source region on the base region; multiple trenches having a longitudinal direction in a first direction penetrating the source region and the base region; a gate electrode in each trench via a gate insulation film; an interlayer insulation film covering the gate electrode and having a contact hole, through which the source region and the base contact layer are exposed; a source electrode coupling with the source region and the base region through the contact hole; a drain electrode on the substrate. The source region and the base contact layer extend along with a second direction perpendicular to the first direction, and are alternately arranged along with the first direction. The contact hole has a longitudinal direction in the first direction.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 19, 2012
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Shinichiro MIYAHARA, Hidefumi Takaya, Masahiro Sugimoto, Jun Morimoto, Yukihiko Watanabe
  • Publication number: 20110309464
    Abstract: A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.
    Type: Application
    Filed: June 20, 2011
    Publication date: December 22, 2011
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Kensaku YAMAMOTO, Naohiro Suzuki, Hidefumi Takaya, Masahiro Sugimoto, Jun Morimoto, Narumasa Soejima, Tsuyoshi Ishikawa, Yukihiko Watanabe
  • Patent number: 8076718
    Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.
    Type: Grant
    Filed: September 28, 2005
    Date of Patent: December 13, 2011
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
  • Publication number: 20110291110
    Abstract: The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.
    Type: Application
    Filed: May 27, 2011
    Publication date: December 1, 2011
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Naohiro SUZUKI, Hideo MATSUKI, Masahiro SUGIMOTO, Hidefumi TAKAYA, Jun MORIMOTO, Tsuyoshi ISHIKAWA, Narumasa SOEJIMA, Yukihiko WATANABE
  • Publication number: 20110220991
    Abstract: A semiconductor device 10 may comprise an element domain 40 and a termination domain 50 that surrounds the element domain 40. The element domain 40 and the termination domain 50 respectively may comprise a second conductive type drift region 18. A gate trench 38 may be provided in the element domain 40. The termination domain 50 may be provided with a termination trench 22 surrounding the element domain. A first conductive type floating region surrounded by the drift region 18 is not provided at a bottom of the gate trench 38, and a first conductive type floating region 20 surrounded by the drift region 18 is provided at a bottom of the termination trench 22.
    Type: Application
    Filed: March 8, 2011
    Publication date: September 15, 2011
    Applicant: Toyota Jidosha Kabushiki Kaisha
    Inventor: Hidefumi Takaya
  • Publication number: 20110203513
    Abstract: In a method of manufacturing a silicon carbide substrate, a defect-containing substrate made of silicon carbide is prepared. The defect-containing substrate has a front surface, a rear surface being opposite to the front surface, and a surface portion adjacent to the front surface. The detect-containing substrate includes a screw dislocation in the surface portion. The front surface of the defect-containing substrate is applied with an external force so that a crystallinity of the surface portion is reduced. After being applied with the external force, the defect-containing substrate is thermally treated so that the crystallinity of the surface portion is recovered.
    Type: Application
    Filed: February 17, 2011
    Publication date: August 25, 2011
    Applicants: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hiroki WATANABE, Yasuo Kitou, Kensaku Yamamoto, Hidefumi Takaya, Masahiro Sugimoto, Jun Morimoto, Yukihiko Watanabe, Narumasa Soejima, Tsuyoshi Ishikawa
  • Patent number: 7999312
    Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: August 16, 2011
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
  • Publication number: 20100224932
    Abstract: A semiconductor 100 has a P? body region and an N? drift region in the order from an upper surface side thereof. A gate trench and a terminal trench passing through the P? body region are formed. The respective trenches are surrounded with P diffusion regions at the bottom thereof. The gate trench builds a gate electrode therein. A P?? diffusion region, which is in contact with the end portion in a lengthwise direction of the gate trench and is lower in concentration than the P? body region and the P diffusion region, is formed. The P?? diffusion region is depleted prior to the P diffusion region when the gate voltage is off. The P?? diffusion region serves as a hole supply path to the P diffusion region when the gate voltage is on.
    Type: Application
    Filed: January 26, 2007
    Publication date: September 9, 2010
    Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi
  • Patent number: 7586151
    Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area. The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of the terminal trench 62.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: September 8, 2009
    Assignees: Toyota Jidosha Kabushiki Kaisha, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
  • Patent number: 7470953
    Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 incorporates the gate electrode 22. A P floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: December 30, 2008
    Assignees: Toyota Jidosha Kabushiki Kaisha, Denso Corporation
    Inventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura
  • Publication number: 20080087951
    Abstract: The invention has an object to provide an insulation gate type semiconductor device and a method for producing the same in which high breakdown voltage and compactness are achieved. The semiconductor device has a gate trench and a P floating region formed in the cell area and has a terminal trench and a P floating region formed in the terminal area. In addition, a terminal trench of three terminal trenches has a structure similar to that of the gate trench, and the other terminal trenches have a structure in which an insulation substance such as oxide silicon is filled. Also, the P floating region 51 is an area formed by implanting impurities from the bottom surface of the gate trench, and the P floating region is an area formed by implanting impurities from the bottom surface of the terminal trench.
    Type: Application
    Filed: September 28, 2005
    Publication date: April 17, 2008
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Hidefumi Takaya, Kimimori Hamada, Kyosuke Miyagi, Yasushi Okura, Akira Kuroyanagi, Norihiko Tokura
  • Publication number: 20080087949
    Abstract: A p-type epitaxial layer is formed on an n+-type substrate and then a buried n-type region is formed at a boundary between the n+-type substrate and the p-type epitaxial layer by ion implantation. Subsequently, a trench is formed so as to reach the n+-type substrate, passing through the p-type epitaxial layer and the buried n-type region. Then, a gate electrode is formed so as to deeply extend into the trench, i.e. to a position opposed to the buried n-type region. In a vertical MOSFET with this structure, when a positive voltage is applied to the gate electrode, an accumulation layer with a low resistance is formed in the buried n-type region, thereby reducing an on-resistance.
    Type: Application
    Filed: September 12, 2007
    Publication date: April 17, 2008
    Applicants: NEC ELECTRONICS CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Michiaki MARUOKA, Kimimori HAMADA, Hidefumi TAKAYA
  • Publication number: 20070241394
    Abstract: The present invention provides an insulated gate semiconductor device which has floating regions around the bottoms of trenches and which is capable of reliably achieving a high withstand voltage. An insulated gate semiconductor device 100 includes a cell area through which current flows and an terminal area which surrounds the cell area. The semiconductor device 100 also has a plurality of gate trenches 21 in the cell area and a plurality of terminal trenches 62 in the terminal area The gate trenches 21 are formed in a striped shape, and the terminal trenches 62 are formed concentrically. In the semiconductor device 100, the gate trenches 21 and the terminal trenches 62 are positioned in a manner that spacings between the ends of the gate trenches 21 and the side of the terminal trench 62 are uniform. That is, the length of the gate trenches 21 is adjusted according to the curvature of the corners of terminal trench 62.
    Type: Application
    Filed: May 11, 2005
    Publication date: October 18, 2007
    Inventors: Hidefumi Takaya, Yasushi Okura, Akira Kuroyanagi, Norihito Tokura
  • Publication number: 20060289928
    Abstract: The invention is intended to present an insulated gate type semiconductor device that can be manufactured easily and its manufacturing method while realizing both higher withstand voltage design and lower on-resistance design. The semiconductor device comprises N+ source region 31, N+ drain region 11, P? body region 41, and N? drift region 12. By excavating part of the upper side of the semiconductor device, a gate trench 21 is formed. The gate trench 21 floating region 51 is provided beneath the gate trench 21. A further trench 35 differing in depth from the gate trench 21 may be formed, a P floating region 54 being provided beneath the trench 25.
    Type: Application
    Filed: October 6, 2004
    Publication date: December 28, 2006
    Inventors: Hidefumi Takaya, Kimimori Hamada, Akira Kuroyanagi, Yasushi Okura, Norihito Tokura