Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

Abstract: A static random access memory (SRAM) cell includes a four-contact polysilicon pitch (4Cpp) fin field effect transistor (FinFET) architecture including a first bit-cell and a second bit cell. The SRAM cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the SRAM cell. The SRAM cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.

Abstract: A cell structure is disclosed. The cell structure includes a first unit comprising a first group of transistors and a first data latch, a second unit comprising a second group of transistors and a second data latch a read port unit comprising a plurality of p-type transistors, a search line and a complementary search line, the search line and the complementary search line function as input of the cell structure, and a master line, the master line functions as an output of the cell structure, the first unit is coupled to the second unit, both the first and the second units are coupled to the read port unit. According to some embodiments, the first data latch comprises a first and a second p-type transistors, a first and a second n-type transistors.

Abstract: A memory array includes a column of cells arranged along a first direction and a bit line extending along the first direction over the column of cells. The column of cells includes a set of memory cells and a set of strap cells. The bit line includes a first conductor in a second conductor. The first conductor extends in the first direction and is in a first conductive layer. The second conductor extends in the first direction and is in a second conductive layer different from the first conductive layer.

Abstract: An integrated circuit and an operating method thereof are provided. The integrated circuit includes memory cells, at least one first word line, second word lines, bit lines and write-assist bit lines. The at least one first word line is electrically connected to at least one row of the memory cells. The second word lines are electrically connected to other rows of the memory cells. Two bit lines are located between a column of the memory cells and two write-assist bit lines. The bit lines and the write-assist bit lines are configured to be electrically disconnected with each other when at least one of the memory cells electrically connected with the at least one first word line is configured to be written, and electrically connected with each other when at least one of the memory cells electrically connected to the second word lines is configured to be written.

Abstract: A static random access memory (SRAM) device includes a first memory array including a plurality of memory cells, each memory cell including a first pass gate transistor with a first threshold voltage connected to a bit line. The SRAM device further includes a second memory array including a plurality of memory cells, each memory cell including a second pass gate transistor with a second threshold voltage connected to the bit line. The SRAM device further includes a peripheral input-output circuit connected to the bit line. The SRAM device still further includes a column of write current tracking cells, each tracking cell disposed within a row of the first memory array and the second memory array, wherein the first memory array is between the peripheral input-output circuit and the second memory array.

Abstract: A memory device is provided. The memory device includes a shift register array having a plurality of shift registers arranged in a matrix of a plurality of rows and a plurality of columns. Each of the plurality of rows comprises a first plurality of shift registers and each of the plurality of columns comprises a second plurality of shift registers. Each of the plurality of rows are associated with a read word line and a write word lines. Each of the plurality of rows are associated with a data input line and a data output line. Each of the plurality of shift arrays comprises a static random access memory.

Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

Abstract: A memory device includes: a memory cell array having a plurality of memory cells, wherein each of the plurality of memory cells includes a first port; a first control circuit disposed on a first side of the memory cell array and arranged to electrically connect to the plurality of first ports; and a second control circuit disposed on a second side of the memory cell array and arranged to electrically connect to the plurality of first ports; wherein the second side is opposite to the first side of the memory cell array.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A semiconductor chip is provided. The semiconductor chip includes a memory cell and a logic cell disposed aside the memory cell, and includes signal and ground lines with the memory and logic cells located therebetween. The memory cell includes first and second active structures extending along a first direction, and includes a storage transmission gate line, first through third gate lines and a read transmission gate line extending along a second direction. The storage transmission gate line includes first and second line segments, which respectively extends across the active structures. The first through third gate lines continuously extend across the first and second active structures. The read transmission gate line includes third and fourth line segments, which respectively extend across the active structures. The first through third gate lines are located between the storage and read transmission gate lines.

Abstract: A memory device includes memory cells and a control circuit. Each memory cell includes a first inverter, a second inverter, a first transistor and a second transistor. The first and second inverters are cross-coupled between a first data node and a second data node. The first transistor has a first control terminal coupled to a wordline, a first connection terminal coupled to a bitline, and a second connection terminal. The second transistor has a second control terminal, a third connection terminal and a fourth connection terminal. The second control terminal is coupled to the first data node. The third connection terminal is coupled to the second connection terminal. The control circuit is coupled to the fourth connection terminal, and is configured to, when the bitline is selected, adjust a voltage level at the fourth connection terminal in response to activation of the wordline.

Abstract: The present disclosure describes various exemplary memory storage devices that can be programmed to bypass one or more memory cells in a bypass mode of operation. The various exemplary memory storage devices can adjust, for example, pull-up or pull-down, the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. In some situations, the various exemplary memory storage devices may introduce an unwanted bias into the electronic data as the electronic data passes through these exemplary memory storage devices in the bypass mode of operation. The various exemplary memory storage devices can pull-down the electronic data and/or pull-up the electronic data as the electronic data is passing through these exemplary memory storage devices in the bypass mode of operation to compensate for this unwanted bias.

Abstract: In some embodiments, a semiconductor memory device includes an array of semiconductor memory cells arranged in rows and columns. The array includes a first segment of memory cells and a second segment of memory cells. A first pair of complementary local bit lines extend over the first segment of memory cells and is coupled to multiple memory cells along a first column within the first segment of memory cells. A second pair of complementary local bit lines extend over the second segment of memory cells and is coupled to multiple memory cells along the first column within the second segment of memory cells. A pair of switches is arranged between the first and second segments of memory cells. The pair of switches is configured to selectively couple the first pair of complementary local bit lines in series with the second pair of complementary local bit lines.

Abstract: Some embodiments relate to an SRAM cell layout including upper and lower cell edges and left and right cell edges. A first power rail extends generally in parallel with and lies along the left cell edge or the right cell edge. The first power rail is coupled to a first power supply. A second power rail extends generally in parallel with the first power rail and is arranged equidistantly between the left and right cell edges. A first bitline extends in parallel with the first power rail and the second power rail and is arranged to a first side of the second power rail. A second bitline, which is complementary to the first bitline, extends in parallel with the first power rail and the second power rail and is arranged to a second side of the second power rail.

Abstract: A semiconductor memory device includes: a column of segments, each segment including bit cells; a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; each of the bit cells being connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and a local write driver included in each segment, each local write driver being connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line; and wherein: the global write driver and each local write driver is connected between the GWB line and the LWB line and between the GWB_bar line and the LWB_bar line.

Abstract: A circuit includes a memory array, a write circuit configured to store data in memory cells of the memory array, a read circuit configured to retrieve the stored data from the memory cells of the memory array, and a computation circuit configured to perform one or more logic operations on the retrieved stored data. The memory array is positioned between the write circuit and the read circuit.