Abstract: Systems and method are provided for a memory circuit. In embodiments, the circuit includes a plurality of memory cells corresponding to a word of data and a global write word line. A plurality of local write lines are connected to a subset of the plurality of memory cells of the word of data. Selection logic is configured to activate a particular subset of memory cells for writing via a particular local write line based on a signal on the global write word line and a selection signal associated with the particular subset of memory cells.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A circuit includes a data register configured to receive a signal including a plurality of data elements, a first selection circuit coupled to the data register, a counter, a second selection circuit coupled to the counter, and an inverter coupled between the counter and the second selection circuit. The data register outputs a plurality of bits of each data element to the first selection circuit, the counter and the inverter generate complementary signals in which sequential data elements have cyclical values that step in opposite directions, the second selection circuit alternatively outputs each of the complementary signals as a selection signal to the first selection circuit, and the first selection circuit, responsive to the selection signal, outputs the pluralities of bits of the data elements in alternating sequential orders.

Abstract: An integrated circuit (IC) package includes a logic die, a substrate, a memory die positioned between the logic die and the substrate, and a power distribution structure configured to electrically couple the logic die to the substrate. The power distribution structure includes a plurality of conductive segments positioned between the logic die and the memory die, a plurality of bump structures positioned between the memory die and the substrate, and a plurality of through-silicon vias (TSVs) electrically coupled to the plurality of conductive segments and the plurality of bump structures, and a TSV of the plurality of TSVs extends through, and is electrically isolated from, a memory macro of the memory die.

Abstract: A memory cell includes a write port and a read port. The write port includes two cross-coupled inverters that form a storage unit. The cross-coupled inverters are connected between a first power source signal line and a second power source signal line. The write port also includes a first local interconnect line in an interconnect layer that is connected to the second power source signal line. The read port includes a transistor that is connected to the storage unit in the write port and to the second power source signal line, and a second local interconnect line in the interconnect layer that is connected to the second power source signal line. The second local interconnect line in the read port is separate from the first local interconnect line in the write port.

Abstract: A memory device includes active regions and gate structures, each of the gate structures is electrically coupled to a first portion of a corresponding active region of the active regions. The memory device includes contact-to-transistor-component structures (MD structures), each of the MD structures is over a second portion of a corresponding active region, and a first MD structure is between adjacent gate structures. The memory device includes via-to-gate/MD (VGD) structures, each of the VGD structures is over to a corresponding gate electrode and MD structure. The memory device includes conductive segments, each of the conductive segments is over and electrically coupled to a corresponding VGD structure. The memory device includes buried contact-to-transistor-component structures (BVD) structures, each of the BVD structures is under a third portion of a corresponding active region.

Abstract: A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.

Abstract: Systems and methods for floating-point processors and methods for operating floating-point processors are provided. A floating-point processor includes a quantizer, a compute-in-memory device, and a decoder. The floating-processor is configured to receive an input array in which the values of the input array are represented in floating-point format. The floating-point processor may be configured to convert the floating-point numbers into integer format so that multiply-accumulate operations can be performed on the numbers. The multiply-accumulate operations generate partial sums, which are in integer format. The partial sums can be accumulated until a full sum is achieved, wherein the full sum can then be converted to floating-point format.

Abstract: A method of forming a memory circuit includes generating a layout design of the memory circuit, and manufacturing the memory circuit based on the layout design. The memory circuit is a four transistor memory cell that includes at least the first pass gate transistor and the first pull up transistor. The generating of the layout design includes generating a first active region layout pattern corresponding to fabricating a first active region of a first pull up transistor, generating a second active region layout pattern corresponding to fabricating a second active region of a first pass gate transistor, and generating a first metal contact layout pattern corresponding to fabricating a first metal contact is electrically coupled to a source of the first pull up transistor. The first metal contact layout pattern extends in a second direction, overlaps a cell boundary of the memory circuit and the first active region layout pattern.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Abstract: An SRAM includes multiple memory cells, each memory cell includes a data storage unit; a data I/O control adapted to input data to, and output data from, a data line (BL); and multiple access controls respectively connected to at least two access control lines (WL's) and adapted to enable and disable the data input and output from the at least two WL's (WX and WY). The access controls are configured to permit data input only when both WL's are in their respective states that permit data input. A method of writing to a group of SRAM cells include sending a first write-enable signal to the cells via a first WL, sending a group of respective second write-enable signals to the respective cells, and, for each of the cells, preventing writing data to the cell if either of the first write-enable signal and respective second write enable signal is in a disable-state.

Abstract: A memory device has a memory array including a memory segment to store weight data, a weight buffer coupled to the memory segment and configured to hold new weight data to be updated in the memory segment, a logic circuit, and a computation circuit coupled to an output of the logic circuit. The logic circuit further has a first input coupled to the memory segment by a bit line, and a second input configured to receive input data. The logic circuit is configured to generate, at the output, intermediate data corresponding to the input data and the weight data read from the memory segment through the bit line. The computation circuit is configured to, based on the intermediate data, generate output data corresponding to a computation performed on the input data and the weight data read from the at least one memory segment.

Abstract: An integrated circuit includes a first encoder, a compute in-memory (CIM) array and a de-encoder. The first encoder is configured to quantize a first received signal into a first signal. The first received signal has a first floating point number format. The first signal has an integer number format. The compute in-memory (CIM) array is coupled to the first encoder. The CIM array is configured to generate a CIM signal in response to at least the first signal. The CIM signal has the integer number format. The de-encoder is coupled to the CIM array, and is configured to generate a first output signal in response to the CIM signal. The first output signal has a second floating point number format.

Abstract: Disclosed herein are related to an integrated circuit to regulate a supply voltage. In one aspect, the integrated circuit includes a metal rail including a first point, at which a first functional circuit is connected, and a second point, at which a second functional circuit is connected. In one aspect, the integrate circuit includes a voltage regulator coupled between the first point of the metal rail and the second point of the metal rail. In one aspect, the voltage regulator senses a voltage at the second point of the metal rail and adjusts a supply voltage at the first point of the metal rail, according to the sensed voltage at the second point of the metal rail.

Abstract: A memory device including: active regions; gate electrodes which are substantially aligned relative to four corresponding track lines such that the memory device has a width of four contacted poly pitch (4 CPP) and are electrically coupled to the active regions; contact-to-transistor-component structures (MD structures) which are electrically coupled to the active regions, and are interspersed among corresponding ones of the gate electrodes; via-to-gate/MD (VGD) structures which are electrically coupled to the gate electrodes and the MD structures; conductive segments which are in a first layer of metallization (M_1st layer), and are electrically coupled to the VGD structures; buried contact-to-transistor-component structures (BVD structures) which are electrically coupled to the active regions; and buried conductive segments which are in a first buried layer of metallization (BM_1st layer), and are electrically coupled to the BVD structures, and correspondingly provide a first reference voltage or a second r

Abstract: A memory macro structure includes a first memory array, a second memory array, a cell activation circuit coupled to the first and second memory arrays and positioned between the first and second memory arrays, a control circuit coupled to the cell activation circuit and positioned adjacent to the cell activation circuit, and a through-silicon via (TSV) extending through one of the cell activation circuit or the control circuit.

Abstract: A memory device is provided. The memory device includes a memory cell and a bit line connected to the memory cell. A negative voltage generator is connected to the bit line. The negative voltage generator, when enabled, is operative to provide a first write path for the bit line. A control circuit is connected to the negative voltage generator and the bit line. The control circuit is operative to provide a second write path for the bit line when the negative voltage generator is not enabled.

Abstract: A memory device is provided. The memory device includes a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns. A first column of the plurality of columns of the matrix includes a first plurality of memory cells of the plurality of memory cells, a first pair of bit lines connected to each of the first plurality of bit cells, and a second pair of bit lines connectable to the first pair of bit lines through a plurality of switches.

Abstract: The present disclosure describes embodiments of a write assist circuit. The write assist circuit can include a control circuit and a voltage generator. The control circuit can be configured to receive memory address information associated with a memory write operation for memory cells. The voltage generator can be configured to provide a reference voltage to one or more bitlines coupled to the memory cells. The voltage generator can include two capacitive elements, where during the memory write operation, (i) one of the capacitive elements can be configured to couple the reference voltage to a first negative voltage, and (ii) based on the memory address information, both capacitive elements can be configured to cumulatively couple the reference voltage to a second negative voltage that is lower than the first negative voltage.

Abstract: A semiconductor memory device includes: a local write bit (LWB) line; a local write bit_bar (LWB_bar) line; a global write bit (GWB) line; a global write bit_bar (GWBL_bar) line; a column of segments, each segment including bit cells that are connected correspondingly between the LWB and LWB_bar lines; and a distributed write driving arrangement including a global write driver and local write drivers included correspondingly in the segments; and the global write driver including a first equalizer circuit, arranged in a switched-coupling between the LWB line and the LWB_bar line, and arranged in a control-coupling with respect to signals correspondingly on the GWB line and the GWB_bar line, and the global write driver and the local write drivers each including first inversion couplings (coupled in parallel between the GWB line and the LWB line) and second inversion couplings (coupled in parallel between the GWB_bar line and the LWB_bar line).