Abstract: [Object] To promptly decode and reproduce content of any encoding formats. [Solving Means] If a TV (1) judges that it cannot decode content to be viewed by a user, the TV (1) asks another apparatus such as a game apparatus (3) or PC (4) whether it can decode the content via a high-speed data line (150) capable of performing bidirectional IP communication in expanded HDMI and transmits the content and decoding request command thereof to an apparatus which has answered that it can perform decoding, via the high-speed data line (150). The game apparatus (3) or the PC (4) which has received the decoding request decodes the content and transmits the decoded content as a baseline signal to the TV (1) via TMDS channels in expanded HDMI so that the content is reproduced.

Abstract: To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected. An HPD signal line (902) has, on an expanded HDMI sink apparatus (402) side circuit, a pull-up resistor (911) between the HPD signal line (902) and a voltage supply and a pull-down resistor (913) between the HPD signal line (902) and the ground, and a reserved line (903) has, on the expanded HDMI sink apparatus (402) side circuit, a pull-down resistor (914) between the reserved line (903) and a ground, and within a new HDMI cable (901), a pull-up resistor (912) between the reserved line (903) and a voltage supply of an expanded HDMI source apparatus (401). The expanded HDMI sink apparatus compares a voltage at a test point (19) on the reserved line (903) on the expanded HDMI sink apparatus (402) side with a reference voltage by using a voltage comparator (916).

Abstract: A television receiver computes a delay time of an image displayed on the television receiver with respect to an audio signal transmitted from the television receiver to an audio amplifier, based on video delay information as EDID data, delay information transported from a disc recorder and information of a time required until audio data received from the disc recorder is transmitted to an audio amplifier. The audio amplifier controls a delay time lasting until the audio responsive to the received audio data is outputted so that the delay time matches the aforementioned delay time. Thereby, the displayed image in the television receiver and the audio output in the audio amplifier are synchronized.

Abstract: A signal transmission system including: a first connector apparatus, and a second connector apparatus that is coupled with the first connector apparatus. The first connector apparatus and the second connector apparatus are coupled together to form an electromagnetic field coupling unit, and a transmission object signal is converted into a radio signal, which is then transmitted through the electromagnetic field coupling unit, between the first connector apparatus and the second connector apparatus.

Abstract: Disclosed herein is a communication centralized control system including one master device; a communication bus; and a plurality of slave devices configured to be connected to the master device by the communication bus, wherein the master device and the plurality of slave devices are capable of bidirectional communication via the communication bus, and different channels are allocated to at least polling communication from the master device to the slave devices and interrupt communication from the slave devices to the master device, and communication is carried out with multiplexing on the same line.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A power storage apparatus, electric device, electric vehicle, and power system are disclosed. In an example embodiment, a power storage apparatus includes a battery block comprising a plurality of battery cells and an isolating unit that enables wireless information transfer regarding battery information of the battery block.

Abstract: A battery system includes a plurality of electronic storage modules serially connected together. Each electronic storage module includes a battery block group including a plurality of battery cells, and a different magnetic core connected to each battery block group.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: A data receiving device, for receiving digital data via a differential signal transmission path made up of two or more channels including one channel of a reference clock, includes a digital data receiver configured to receive various data channel signals transmitted from the transmitter side to the differential signal transmission path, a reference clock receiver configured to receive a reference clock transmitted from the transmitter side to the differential signal transmission path, and a transmission loss rate determining unit configured to determine between degree of magnitudes of transmission loss with the reference clock, based on waveform deterioration resulting from the reference clock receiving at the reference clock receiving unit having passed through the differential signal transmission path.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source performs bidirectional IP communication with an HDMI (R) sink using a CEC line and a signal line, a switching control unit controls a switch so that, when data is transmitted, the switch selects a constituent signal forming a differential signal output from a converting unit and, when data is transmitted, the switch selects a constituent signal forming a differential signal output from a receiver. When bidirectional communication is performed using only the CEC line, the switching control unit controls the switch so that the CEC signal output from the HDMI (R) source or the receiver is selected. The present invention is applicable to, for example, HDMI (R).

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source 71 performs bidirectional IP communication with an HDMI (R) sink 72 using a CEC line 84 and a signal line 141, a switching control unit 121 controls a switch 133 so that, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a converting unit 131 and, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a receiver 82. When bidirectional communication is performed using only the CEC line 84, the switching control unit 121 controls the switch 133 so that the CEC signal output from the HDMI (R) source 71 or the receiver 82 is selected. The present invention is applicable to, for example, HDMI (R).

Abstract: A video display device includes: connectors to which cables transmitting video signals are connected; a display panel displaying video by the video signal inputted to the connector from an external device through the cable; a display control unit displaying connector indications indicating the connectors on the display panel; a cable detection unit outputting a step waveform signal to the connector and detecting connection/disconnection of the cable to the connector based on a reflected signal of the step waveform signal, and wherein the display control unit changes the appearance of the connector indications displayed on the display panel according to a detection output of the cable detection unit.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source performs bidirectional IP communication with an HDMI (R) sink using a CEC line and a signal line, a switching control unit controls a switch so that, when data is transmitted, the switch selects a constituent signal forming a differential signal output from a converting unit and, when data is transmitted, the switch selects a constituent signal forming a differential signal output from a receiver. When bidirectional communication is performed using only the CEC line, the switching control unit controls the switch so that the CEC signal output from the HDMI (R) source or the receiver is selected. The present invention is applicable to, for example, HDMI (R).

Abstract: A communication system includes a transmission apparatus for transmitting a plurality of serial data signals that are synchronized in phase with one another and a clock signal that is synchronized in frequency with the serial data signals; and a receiving apparatus for receiving a plurality of serial data signals and the clock signal transmitted from the transmission apparatus. The receiving apparatus includes a phase synchronization circuit configured to roughly adjust the frequency in accordance with the received clock signal and then generate a reproduction clock that is synchronized in phase with one serial data signal among the plurality of serial data signals, and a phase shifter configured to shift the phase from the reproduction clock and lock the phase to another serial signal.

Abstract: A method of manufacturing a semiconductor device capable of preventing a cut portion from becoming chipped when dicing. The method of manufacturing a semiconductor device includes preparing a semiconductor wafer having an upper surface (first surface) including a plurality of device regions and partition regions for dividing the plurality of device regions, and a lower surface (second surface) opposite from the upper surface (first surface), forming upper layer wires on the device regions of the upper surface (first surface), etching the semiconductor wafer from a side of the lower surface (second surface) to form a through hole through which the upper layer wire is exposed, and to form a groove in a region of the lower surface (second surface) corresponding to the partition region of the upper surface (first surface), and dicing the semiconductor wafer to form individual device regions.