Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.

Abstract: Disclosed herein is a driver amplifier circuit, including: a first current source transistor of a first conductivity type, and a second current source transistor of the first conductivity type, control voltages being supplied to gates of the first current source transistor and the second current source transistor, respectively; a first switching transistor of the first conductivity type, and a second switching transistor of the first conductivity type; a third switching transistor of a second conductivity type, and a fourth switching transistor of the second conductivity type; first, second, third, and fourth resistor elements; and a first output node and a second output node.

Abstract: The light emitting device control circuit device 100 in accordance with the disclosure includes a power source V1, a transistor TR1, a light emitting unit EU1, switches S1 to S17, constant current sources CC1 to CC17, and a controller 110. A switching voltage Vs1 is supplied from the controller 110 to turn ON or turn OFF the transistor TR intermittently, a pulse voltage is supplied to a pulse voltage supplying line Y1 connected to a drain terminal D of the transistor TR1. The driving signals SP1 to SP17 are sequentially supplied to the switches S1 to S17 to turn ON or turn OFF them (i.e., time division drive). The light emitting devices A1 to A17 are driven sequentially by a pulse current (i.e., time division drive) when a high voltage is supplied to the pulse voltage supplying line Y1 and when the driving signals SP1 to SP17 are turned ON.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A differential includes first and second current mirror circuits that provide the gates of slave transistors with gate voltages of master transistors via a voltage follower where a slew rate at a rise time is equal to a slew rate at a fall time. Thus, when the master current is increased or decreased, an incremental change in slave current and a decremental change in slave current are symmetrical with each other. The use of such current mirrors in a differential manner leads to no generation of common mode noise even in these changes.

Abstract: The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source 71 performs bidirectional IP communication with an HDMI (R) sink 72 using a CEC line 84 and a signal line 141, a switching control unit 121 controls a switch 133 so that, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a converting unit 131 and, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a receiver 82. When bidirectional communication is performed using only the CEC line 84, the switching control unit 121 controls the switch 133 so that the CEC signal output from the HDMI (R) source 71 or the receiver 82 is selected. The present invention is applicable to, for example, HDMI (R).

Abstract: Disclosed herein is a communication centralized control system including one master device; a communication bus; and a plurality of slave devices configured to be connected to the master device by the communication bus, wherein the master device and the plurality of slave devices are capable of bidirectional communication via the communication bus, and different channels are allocated to at least polling communication from the master device to the slave devices and interrupt communication from the slave devices to the master device, and communication is carried out with multiplexing on the same line.

Abstract: The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source 71 performs bidirectional IP communication with an HDMI (R) sink 72 using a CEC line 84 and a signal line 141, a switching control unit 121 controls a switch 133 so that, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a converting unit 131 and, when data is transmitted, the switch 133 selects a constituent signal forming a differential signal output from a receiver 82. When bidirectional communication is performed using only the CEC line 84, the switching control unit 121 controls the switch 133 so that the CEC signal output from the HDMI (R) source 71 or the receiver 82 is selected. The present invention is applicable to, for example, HDMI (R).

Abstract: A differential drive circuit includes at least a first or second drive system. The first drive system has first and second field effect transistors, first and second resistors, and first and second circuits controlling the source voltages of the first and second field effect transistors to equal first and second drive target voltages, the first and second field effect transistors having sources connected to a power potential via the first and second resistors, respectively. The second drive system has third and fourth field effect transistors, third and fourth resistors, and third and fourth circuits controlling the source voltages of the third and fourth field effect transistors to equal third and fourth drive target voltages, the third and fourth field effect transistors having sources connected to a reference potential via the third and fourth resistors, respectively. A common-mode voltage is driven to form a constant differential signal across a load resistance.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: [Object] To discriminate whether a cable in conformity with a conventional standard or a cable in conformity with a new standard is connected. [Solving Means] An HPD signal line (902) has, on an expanded HDMI sink apparatus (402) side circuit, a pull-up resistor (911) between the HPD signal line (902) and a voltage supply and a pull-down resistor (913) between the HPD signal line (902) and the ground, and a reserved line (903) has, on the expanded HDMI sink apparatus (402) side circuit, a pull-down resistor (914) between the reserved line (903) and a ground, and within a new HDMI cable (901), a pull-up resistor (912) between the reserved line (903) and a voltage supply of an expanded HDMI source apparatus (401). The expanded HDMI sink apparatus compares a voltage at a test point (19) on the reserved line (903) on the expanded HDMI sink apparatus (402) side with a reference voltage by using a voltage comparator (916).

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: The present invention provides a data transfer system including a data transmitter and a data receiver. The data transmitter converts a plurality of bits of transmission parallel data into serial data and generates a multi-level logic signal representing a plurality of bits of information in one symbol, the information being obtained by combining the serial data with a word clock as one-bit information. The word clock indicates a word delimiter in the serial data. The data receiver receives the transmitted multi-level logic signal, extracts the serial data and the word clock from the signal, and reproduces the parallel data based on the extracted word clock. In the data transfer system, a multi-bit digital signal can be transmitted as one signal including a word clock. Thus, components and mounting space to be allocated to transfer can be reduced.

Abstract: Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.

Abstract: [Object] To allow a contents list of a video camera recorder to be smoothly displayed on a television receiver and improve the performance of a selecting operation on video content by a user. [Solving Means] A video camera recorder (source device) 10A and a television receiver (sink device) 30A are connected through an HDMI cable 1. The video camera recorder 10A is provided with an HDMI transmission unit (HDMI TX) 28 and a high-speed data line I/F 28A. The television receiver 30A is provided with an HDMI reception unit (HDMI RX) 32 and a high-speed data line I/F 32A. In response to a transmission request from the television receiver 30A side, the video camera recorder 10A transmits, at high speed, additional information (contents list and thumbnail data) to the television receiver 30A by using a high-speed data line constituted by specific lines of the HDMI cable 1.

Abstract: The present invention relates to a communication system, a transmitter, a receiver, a communication method, a program, and a communication cable for providing high-speed bidirectional communication while maintaining compatibility. When an HDMI (R) source performs bidirectional IP communication with an HDMI (R) sink using a CEC line and a signal line, a switching control unit controls a switch so that, when data is transmitted, the switch selects a constituent signal forming a differential signal output from a converting unit and, when data is transmitted, the switch selects a constituent signal forming a differential signal output from a receiver. When bidirectional communication is performed using only the CEC line, the switching control unit controls the switch so that the CEC signal output from the HDMI (R) source or the receiver is selected. The present invention is applicable to, for example, HDMI (R).

Abstract: A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.

Abstract: A television receiver 250 computes a delay time T2a? of a image displayed on the television receiver 250 with respect to an audio signal transmitted from the television receiver 250 to an audio amplifier 310, based on video delay information (T2v) as EDID data, delay information (T4a) transported from a disc recorder 210 and information of a time T2c required until audio data received from the disc recorder 210 is transmitted to an audio amplifier 310. The audio amplifier 310 controls a delay time lasting until the audio responsive to the received audio data is outputted so that the delay time matches the aforementioned delay time T2a?. Thereby, the displayed image in the television receiver 250 and the audio output in the audio amplifier 310 are synchronized.