Patents by Inventor Hidekazu Miyairi

Hidekazu Miyairi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9318512
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: April 19, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Shunpei Yamazaki
  • Patent number: 9312156
    Abstract: A thin film transistor includes a gate electrode; a gate insulating layer which is provided to cover the gate electrode; a semiconductor layer which is provided over the gate insulating layer to overlap with the gate electrode; an impurity semiconductor layer which is partly provided over the semiconductor layer and which forms a source region and a drain region; and a wiring layer which is provided over the impurity semiconductor layer, where a width of the source region and the drain region is narrower than a width of the semiconductor layer, and where the width of the semiconductor layer is increased at least in a portion between the source region and the drain region.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: April 12, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hidekazu Miyairi
  • Publication number: 20160087107
    Abstract: A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided.
    Type: Application
    Filed: November 30, 2015
    Publication date: March 24, 2016
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Yutaka OKAZAKI, Hidekazu MIYAIRI
  • Patent number: 9293595
    Abstract: A manufacturing method of a semiconductor device having a stacked structure in which a lower layer is exposed is provided without increasing the number of masks. A source electrode layer and a drain electrode layer are formed by forming a conductive film to have a two-layer structure, forming an etching mask thereover, etching the conductive film using the etching mask, and performing side-etching on an upper layer of the conductive film in a state where the etching mask is left so that part of a lower layer is exposed. The thus formed source and drain electrode layers and a pixel electrode layer are connected in a portion of the exposed lower layer. In the conductive film, the lower layer and the upper layer may be a Ti layer and an Al layer, respectively. The plurality of openings may be provided in the etching mask.
    Type: Grant
    Filed: January 28, 2015
    Date of Patent: March 22, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takafumi Mizoguchi
  • Publication number: 20160079438
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Application
    Filed: November 19, 2015
    Publication date: March 17, 2016
    Inventors: Hidekazu MIYAIRI, Kengo AKIMOTO, Yasuo NAKAMURA
  • Patent number: 9275585
    Abstract: Input of image signals to part of a plurality of pixels included in a particular region of a pixel portion and supply of light to part of another plurality of pixels which is different from the part are performed concurrently. Therefore, it is not necessary to provide a period in which light is supplied to all of the plurality of pixels included in the region after the image signals are input thereto. In other words, it is possible to start input of the next image signals to all of the plurality of pixels included in the region just after the image signals are input thereto. Accordingly, it is possible to increase the input frequency of the image signals. As a result, it is possible to suppress deteriorations of display caused in the field-sequential liquid crystal display device.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: March 1, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Hiroyuki Miyake, Kouhei Toyotaka, Susumu Kawashima
  • Patent number: 9257562
    Abstract: It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated. A thermal expansion coefficient of the substrate is 6×10?7/° C. to 38×10?7/° C., preferably 6×10?7/° C. to 31.8×10?7/° C. Next, the layer including the semiconductor film is irradiated with a laser beam to crystallize the semiconductor film so as to form a crystalline semiconductor film. Total stress of the layer including the semiconductor film is ?500 N/m to +50 N/m, preferably ?150 N/m to 0 N/m after the heating step.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: February 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akihisa Shimomura, Hidekazu Miyairi, Fumito Isaka, Yasuhiro Jinbo, Junya Maruyama
  • Patent number: 9257561
    Abstract: To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: February 9, 2016
    Assignee: Semiconductor Energy Laboratory Co., LTD.
    Inventor: Hidekazu Miyairi
  • Patent number: 9236456
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: January 12, 2016
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
  • Patent number: 9230826
    Abstract: A method for etching is provided in which the etching selectivity of an amorphous semiconductor film to a crystalline semiconductor film is high. Part of a stacked semiconductor film in which an amorphous semiconductor film is provided on a crystalline semiconductor film is etched using a mixed gas of a Br-based gas, a F-based gas, and an oxygen gas, so that part of the crystalline semiconductor film provided in the stacked semiconductor film is exposed. Reduction in the film thickness of the exposed portion can be suppressed by performing the etching in such a manner. Moreover, when etching for forming a back channel portion of a thin film transistor is performed with the method for etching, favorable electric characteristics of the thin film transistor can be obtained. An insulating layer is preferably provided over the thin film transistor.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinya Sasagawa, Hiroshi Fujiki, Shinobu Furukawa, Hidekazu Miyairi
  • Patent number: 9219158
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: December 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Kengo Akimoto, Shunpei Yamazaki
  • Publication number: 20150349099
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Application
    Filed: August 6, 2015
    Publication date: December 3, 2015
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Kengo AKIMOTO, Kojiro SHIRAISHI
  • Publication number: 20150348909
    Abstract: Provided is a semiconductor device that occupies a small area, a highly integrated semiconductor device, or a semiconductor device with high productivity. To fabricate an integrated circuit, a first insulating film is formed over a p-channel transistor; a transistor including an oxide semiconductor is formed over the first insulating film; a second insulating film is formed over the transistor; an opening, that is, a contact hole part of a sidewall of which is formed of the oxide semiconductor of the transistor, is formed in the first insulating film and the second insulating film; and an electrode connecting the p-channel transistor and the transistor including an oxide semiconductor to each other is formed.
    Type: Application
    Filed: March 13, 2015
    Publication date: December 3, 2015
    Inventors: Shunpei YAMAZAKI, Hidekazu MIYAIRI, Shinya SASAGAWA
  • Publication number: 20150348997
    Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.
    Type: Application
    Filed: September 17, 2014
    Publication date: December 3, 2015
    Inventors: Shinya Sasagawa, Hidekazu Miyairi, Shunpei Yamazaki, Motomu Kurata
  • Publication number: 20150349127
    Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.
    Type: Application
    Filed: September 17, 2014
    Publication date: December 3, 2015
    Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
  • Publication number: 20150349128
    Abstract: A semiconductor device including an insulator, a first conductor as a source electrode, a second conductor as a drain electrode, a third conductor as a gate electrode, and an island-shaped semiconductor is provided. The first conductor includes a first side surface, a second side surface, and a third side surface. The second conductor includes a fourth side surface. The first conductor and the second conductor are positioned to make the first side surface and the fourth side surface face each other. The first conductor includes a first corner portion between the first side surface and the second side surface and a second corner portion between the second side surface and the third side surface. The first corner portion includes a portion having a smaller radius of curvature than the second corner portion.
    Type: Application
    Filed: May 22, 2015
    Publication date: December 3, 2015
    Inventor: Hidekazu MIYAIRI
  • Patent number: 9202925
    Abstract: A structure is employed in which a first protective insulating layer; an oxide semiconductor layer over the first protective insulating layer; a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer; a gate insulating layer that is over the source electrode and the drain electrode and overlaps with the oxide semiconductor layer; a gate electrode that overlaps with the oxide semiconductor layer with the gate insulating layer provided therebetween; and a second protective insulating layer that covers the source electrode, the drain electrode, and the gate electrode are included. Furthermore, the first protective insulating layer and the second protective insulating layer each include an aluminum oxide film that includes an oxygen-excess region, and are in contact with each other in a region where the source electrode, the drain electrode, and the gate electrode are not provided.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: December 1, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Yutaka Okazaki, Hidekazu Miyairi
  • Publication number: 20150323823
    Abstract: A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.
    Type: Application
    Filed: May 13, 2015
    Publication date: November 12, 2015
    Inventors: Shunpei YAMAZAKI, Takeshi OSADA, Hidekazu MIYAIRI, Yasuhiro JINBO
  • Patent number: 9178071
    Abstract: Provided is a method for manufacturing a semiconductor device with fewer masks and in a simple process. A gate electrode is formed. A gate insulating film, a semiconductor film, an impurity semiconductor film, and a conductive film are stacked in this order, covering the gate electrode. A source electrode and a drain electrode are formed by processing the conductive film. A source region, a drain region, and a semiconductor layer, an upper part of a portion of which does not overlap with the source region and the drain region is removed, are formed by processing the upper part of the semiconductor film, while the impurity semiconductor film is divided. A passivation film over the gate insulating film, the semiconductor layer, the source region, the drain region, the source electrode, and the drain electrode are formed. An etching mask is formed over the passivation film.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: November 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Koji Dairiki, Shunpei Yamazaki, Ryo Arasawa
  • Patent number: 9178069
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: November 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba