Patents by Inventor Hidekazu Miyairi

Hidekazu Miyairi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9176353
    Abstract: An object is to propose a method of manufacturing, with high mass productivity, liquid crystal display devices having thin film transistors with highly reliable electric characteristics. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: November 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Hideaki Kuwabara, Hajime Kimura, Hidekazu Miyairi, Yoshiyuki Kurokawa, Satoshi Kobayashi
  • Patent number: 9166058
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: October 20, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Kengo Akimoto, Yasuo Nakamura
  • Patent number: 9159781
    Abstract: Provided is a method for manufacturing a semiconductor device, in which a degradation of characteristics of a thin film transistor can be suppressed by performing plasma oxidation treatment on a gate insulating film containing nitrogen. An embodiment of the present invention is a method for manufacturing a semiconductor device comprising a thin film transistor including a gate electrode, a gate insulating film containing nitrogen, and a channel region in microcrystalline semiconductor films. The method includes the steps of performing plasma treatment on the gate insulating film in an oxidizing gas atmosphere containing hydrogen and an oxidizing gas containing an oxygen atom, and forming the microcrystalline semiconductor film over the gate insulating film. Formula (1), a/b?2, and Formula (2), b>0, are satisfied, where the amount of hydrogen and the amount of the oxidizing gas in the oxidizing gas atmosphere are a and b, respectively.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: October 13, 2015
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Kanta Abe, Hidekazu Miyairi, Tetsuhiro Tanaka, Takashi Ienaga, Yoshitaka Yamamoto
  • Publication number: 20150255490
    Abstract: Provided is a semiconductor device suitable for miniaturization and higher density. The semiconductor device includes a first transistor, a second transistor overlapping with the first transistor, a capacitor overlapping with the second transistor, and a first wiring electrically connected to the capacitor. The first wiring includes a region overlapping with an electrode of the second transistor. The first transistor, the second transistor, and the capacitor are electrically connected to one another. A channel of the first transistor includes a single crystal semiconductor. A channel of the second transistor includes an oxide semiconductor.
    Type: Application
    Filed: March 4, 2015
    Publication date: September 10, 2015
    Inventor: Hidekazu MIYAIRI
  • Publication number: 20150255492
    Abstract: To provide a semiconductor device including a small-area circuit with high withstand voltage, an oxide semiconductor (OS) transistor is used as some of transistors included in a circuit handling an analog signal in a circuit to which high voltage is applied. The use of an OS transistor with high withstand voltage as a transistor requiring resistance to high voltage enables the circuit area to be reduced without lowering the performance, as compared to the case using a Si transistor. Furthermore, an OS transistor can be provided over a Si transistor, so that transistors using different semiconductor layers can be stacked, resulting in a much smaller circuit area.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 10, 2015
    Inventors: Kei TAKAHASHI, Hiroyuki Miyake, Hidekazu Miyairi
  • Publication number: 20150249147
    Abstract: To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.
    Type: Application
    Filed: May 14, 2015
    Publication date: September 3, 2015
    Inventors: Hidekazu MIYAIRI, Kengo AKIMOTO, Yasuo NAKAMURA
  • Patent number: 9111804
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20150228677
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, a problem of higher manufacturing cost, because it is difficult to mount an IC chip including a driver circuit for driving of the gate and signal lines by bonding or the like. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver portion are provided over the same substrate, manufacturing cost can be reduced.
    Type: Application
    Filed: April 23, 2015
    Publication date: August 13, 2015
    Inventors: Hidekazu MIYAIRI, Takeshi OSADA, Shunpei YAMAZAKI
  • Patent number: 9105659
    Abstract: An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
    Type: Grant
    Filed: July 17, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Akiharu Miyanaga, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20150221778
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. The pixel portion and the driver portion are provided over the same substrate, whereby manufacturing cost can be reduced.
    Type: Application
    Filed: April 2, 2015
    Publication date: August 6, 2015
    Inventors: Hidekazu MIYAIRI, Takeshi OSADA, Kengo AKIMOTO, Shunpei YAMAZAKI
  • Publication number: 20150214256
    Abstract: To provide a semiconductor device that is suitable for miniaturization. The semiconductor device includes a first transistor, a second transistor over the first transistor, an insulating film between the first transistor and the second transistor, a wiring between the first transistor and the insulating film, and an electrode. The electrode and the wiring partly overlap each other. The insulating film has a function of reducing diffusion of water or hydrogen. A channel in the first transistor includes a single crystal semiconductor. A channel in the second transistor includes an oxide semiconductor. A gate electrode of the second transistor includes the same material as that included in the electrode.
    Type: Application
    Filed: January 26, 2015
    Publication date: July 30, 2015
    Inventor: Hidekazu MIYAIRI
  • Patent number: 9087745
    Abstract: It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 21, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hidekazu Miyairi, Kengo Akimoto, Kojiro Shiraishi
  • Publication number: 20150187898
    Abstract: A novel semiconductor device with a transistor using an oxide semiconductor film, in which a conductive film including Cu is used as a wiring or the like, is provided. The semiconductor device includes a first insulating film, an oxide semiconductor over the first insulating film, a gate electrode overlapping the oxide semiconductor with a gate insulating film positioned therebetween, a second insulating film in contact with a side surface of the gate electrode, and a third insulating film in contact with a top surface of the gate electrode. The gate electrode includes a Cu—X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, Ti, Zr, Mg, Ca, or a mixture of two or more of these elements).
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventor: Hidekazu Miyairi
  • Publication number: 20150187823
    Abstract: A semiconductor device that is suitable for miniaturization is provided. Alternatively, a highly reliable semiconductor device is provided. A semiconductor device including a capacitor and a transistor is provided. In the semiconductor device, the transistor includes a semiconductor layer, the semiconductor layer is positioned over the capacitor, and the capacitor includes a first electrode that is electrically connected to the transistor.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventors: Hidekazu Miyairi, Shunpei Yamazaki
  • Publication number: 20150187814
    Abstract: A semiconductor device that is suitable for miniaturization is provided. A semiconductor device including a first element, a first insulator over the first element, a first barrier film over the first insulator, a first conductor over the first barrier film, a second barrier film over the first conductor, a second insulator over the second barrier film, and a semiconductor over the second insulator is provided. The first conductor is surrounded by the first barrier film and the second barrier film.
    Type: Application
    Filed: December 22, 2014
    Publication date: July 2, 2015
    Inventors: Hidekazu Miyairi, Shinya Sasagawa
  • Patent number: 9069202
    Abstract: Provided are a liquid crystal display device with horizontal electric field mode, in which a decrease in driving speed can be suppressed by reducing the resistance of a wiring even when the number of pixels is increased, and a manufacturing method thereof. One of a scan wiring and a signal wiring is divided in an intersection portion where the scan wiring and the signal wiring intersect with each other, and the separated wirings are connected with a connection electrode positioned over a thick insulating film. Accordingly, parasitic capacitance at the intersection portion can be reduced, preventing the decrease in the driving speed. The connection electrode is formed at the same time as formation of a pixel electrode and a common electrode using a low-resistance metal, which contributes to the reduction in manufacturing process of the liquid crystal display device.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 30, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Tetsuji Ishitani, Daisuke Kubota, Toshiyuki Isa, Kouhei Toyotaka, Susumu Kawashima
  • Publication number: 20150179813
    Abstract: It is an object to provide a method of manufacturing a crystalline silicon device and a semiconductor device in which formation of cracks in a substrate, a base protective film, and a crystalline silicon film can be suppressed. First, a layer including a semiconductor film is formed over a substrate, and is heated. A thermal expansion coefficient of the substrate is 6×10?7/° C. to 38×10?7/° C., preferably 6×10?7/° C. to 31.8×10?7/° C. Next, the layer including the semiconductor film is irradiated with a laser beam to crystallize the semiconductor film so as to form a crystalline semiconductor film. Total stress of the layer including the semiconductor film is ?500 N/m to +50 N/m, preferably ?150 N/m to 0 N/m after the heating step.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Inventors: Akihisa SHIMOMURA, Hidekazu MIYAIRI, Fumito ISAKA, Yasuhiro JINBO, Junya MARUYAMA
  • Patent number: 9057924
    Abstract: An object is to propose a method of manufacturing, with high mass productivity, liquid crystal display devices having thin film transistors with highly reliable electric characteristics. In a liquid crystal display device having an inverted staggered thin film transistor, the inverted staggered thin film transistor is formed as follows: a gate insulating film is formed over a gate electrode; a microcrystalline semiconductor film which functions as a channel formation region is formed over the gate insulating film; a buffer layer is formed over the microcrystalline semiconductor film; a pair of source and drain regions are formed over the buffer layer; and a pair of source and drain electrodes are formed in contact with the source and drain regions so as to expose a part of the source and drain regions.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: June 16, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yukie Suzuki, Hideaki Kuwabara, Hajime Kimura, Hidekazu Miyairi, Yoshiyuki Kurokawa, Satoshi Kobayashi
  • Patent number: 9054203
    Abstract: As a display device has a higher definition, the number of pixels, gate lines, and signal lines are increased. When the number of the gate lines and the signal lines are increased, there occurs a problem that it is difficult to mount an IC chip including a driver circuit for driving the gate and signal lines by bonding or the like, whereby manufacturing cost is increased. A pixel portion and a driver circuit for driving the pixel portion are provided over the same substrate, and at least part of the driver circuit includes a thin film transistor using an oxide semiconductor interposed between gate electrodes provided above and below the oxide semiconductor. Therefore, when the pixel portion and the driver circuit are provided over the same substrate, manufacturing cost can be reduced.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: June 9, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidekazu Miyairi, Takeshi Osada, Kengo Akimoto, Shunpei Yamazaki
  • Patent number: 9048147
    Abstract: A display device of which frame can be narrowed and of which display characteristics are excellent is provided. In a display device including a switch portion or a buffer portion, a logic circuit portion, and a pixel portion, the pixel portion includes a first inverted staggered TFT and a pixel electrode which is connected to a wiring of the first inverted staggered TFT, the switch portion or the buffer portion includes a second inverted staggered TFT in which a first insulating layer, a semiconductor layer, and a second insulating layer are interposed between a first gate electrode and a second gate electrode, the logic circuit portion includes an inverter circuit including a third inverted staggered thin film transistor and a fourth inverted staggered thin film transistor, and the first to the fourth inverted staggered thin film transistors have the same polarity. The inverter circuit may be an EDMOS circuit.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 2, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takeshi Osada, Hidekazu Miyairi, Yasuhiro Jinbo