Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.

Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.

Abstract: An example apparatus includes first and second memory cell arrays arranged in a first direction; and a plurality of first and second sub word line drivers, a plurality of main word line drivers, and a plurality of level shift circuits each arranged on an intermediate region between the first and second memory cell arrays. The first and second sub word line drivers are arranged in a second direction and along the first and second memory cell array, respectively. The main word line drivers are arranged in the second direction and adjacently along the plurality of second sub word line drivers. The level shift circuits are arranged in the second direction and adjacently along the plurality of first sub word line drivers. The level shift circuits are configured to provide voltage-level-shifted signals to the plurality of main word line drivers, respectively.

Abstract: Apparatuses, systems, and methods for partial array self refresh masking. A memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (PASR) logic which provides a mask signal. The mask signal may be deactivated responsive to an access operation performed on the associated segment. While the mask signal is deactivated, self-refresh operations are performed on the segment. A period of time after deactivating the mask signal, the mask signal may be reactivated.

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

Abstract: Apparatuses, systems, and methods for partial array self refresh masking. A memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (PASR) logic which provides a mask signal. The mask signal may be deactivated responsive to an access operation performed on the associated segment. While the mask signal is deactivated, self-refresh operations are performed on the segment. A period of time after deactivating the mask signal, the mask signal may be reactivated.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.

Abstract: Apparatuses, systems, and methods for partial array self refresh masking. A memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (PASR) logic which provides a mask signal. The mask signal may be deactivated responsive to an access operation performed on the associated segment. While the mask signal is deactivated, self-refresh operations are performed on the segment. A period of time after deactivating the mask signal, the mask signal may be reactivated.

Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.

Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.

Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.

Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.

Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.