Patents by Inventor Hidekazu Noguchi
Hidekazu Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240071460Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.Type: ApplicationFiled: November 9, 2023Publication date: February 29, 2024Inventor: Hidekazu Noguchi
-
Publication number: 20230410874Abstract: Apparatuses, systems, and methods for partial array self refresh masking. A memory bank may be divided into a number of segments, each of which is associated with partial-array self-refresh (PASR) logic which provides a mask signal. The mask signal may be deactivated responsive to an access operation performed on the associated segment. While the mask signal is deactivated, self-refresh operations are performed on the segment. A period of time after deactivating the mask signal, the mask signal may be reactivated.Type: ApplicationFiled: May 31, 2022Publication date: December 21, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: YUKIMI MORIMOTO, YOSHIO MIZUKANE, HIDEKAZU NOGUCHI
-
Publication number: 20230402070Abstract: Apparatuses and methods for controlling access to memory cell matrices are described. An example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. One section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Applicant: Micron Technology, Inc.Inventors: MANAMI SENOO, HIDEKAZU NOGUCHI, YOSHIO MIZUKANE
-
Patent number: 11721389Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.Type: GrantFiled: September 19, 2022Date of Patent: August 8, 2023Assignee: Micron Technology, Inc.Inventors: Toshiyuki Sato, Hidekazu Noguchi
-
Publication number: 20230013417Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.Type: ApplicationFiled: September 19, 2022Publication date: January 19, 2023Applicant: Micron Technology, Inc.Inventors: Toshiyuki Sato, Hidekazu Noguchi
-
Patent number: 11557331Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.Type: GrantFiled: September 23, 2020Date of Patent: January 17, 2023Assignee: Micron Technology, Inc.Inventors: Shingo Mitsubori, Hidekazu Noguchi
-
Publication number: 20230005525Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.Type: ApplicationFiled: September 6, 2022Publication date: January 5, 2023Applicant: MICRON TECHNOLOGY, INC.Inventor: HIDEKAZU NOGUCHI
-
Patent number: 11468937Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.Type: GrantFiled: November 9, 2020Date of Patent: October 11, 2022Assignee: Micron Technology, Inc.Inventor: Hidekazu Noguchi
-
Patent number: 11450378Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.Type: GrantFiled: September 29, 2020Date of Patent: September 20, 2022Assignee: Micron Technology, Inc.Inventors: Toshiyuki Sato, Hidekazu Noguchi
-
Patent number: 11356081Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.Type: GrantFiled: September 6, 2019Date of Patent: June 7, 2022Assignee: Micron Technology, Inc.Inventor: Hidekazu Noguchi
-
Publication number: 20220148646Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.Type: ApplicationFiled: November 9, 2020Publication date: May 12, 2022Applicant: MICRON TECHNOLOGY, INC.Inventor: HIDEKAZU NOGUCHI
-
Patent number: 11322192Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.Type: GrantFiled: February 28, 2020Date of Patent: May 3, 2022Assignee: Micron Technology, Inc.Inventors: Masaru Morohashi, Hidekazu Noguchi
-
Publication number: 20220101910Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.Type: ApplicationFiled: September 29, 2020Publication date: March 31, 2022Applicant: Micron Technology, Inc.Inventors: Toshiyuki Sato, Hidekazu Noguchi
-
Publication number: 20220093165Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.Type: ApplicationFiled: September 23, 2020Publication date: March 24, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: SHINGO MITSUBORI, HIDEKAZU NOGUCHI
-
Patent number: 11257529Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.Type: GrantFiled: November 20, 2020Date of Patent: February 22, 2022Assignee: Micron Technology, Inc.Inventors: Yangsung Joo, Hidekazu Noguchi
-
Patent number: 11222686Abstract: Refresh commands may be provided at random intervals from a memory controller to a memory device. In some examples, refresh requests may be provided at random intervals which may be used to provide refresh commands from the memory controller to the memory device at random intervals. In some examples, an average time interval between refresh requests may be equal to a refresh interval of the memory device. In some examples, a maximum number of times the memory controller may postpone providing a refresh command to the memory device may be a random number. In some examples, a maximum value of the random number may be based, at least in part, on a minimum number of refresh commands required within a time interval by the memory device.Type: GrantFiled: November 12, 2020Date of Patent: January 11, 2022Assignee: Micron Technology, Inc.Inventor: Hidekazu Noguchi
-
Publication number: 20210166752Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.Type: ApplicationFiled: February 12, 2021Publication date: June 3, 2021Applicant: MICRON TECHNOLOGY, INC.Inventor: Hidekazu Noguchi
-
Patent number: 10957377Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.Type: GrantFiled: December 26, 2018Date of Patent: March 23, 2021Assignee: Micron Technology, Inc.Inventor: Hidekazu Noguchi
-
Publication number: 20210075408Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.Type: ApplicationFiled: September 6, 2019Publication date: March 11, 2021Applicant: MICRON TECHNOLOGY, INC.Inventor: Hidekazu Noguchi
-
Publication number: 20210074341Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.Type: ApplicationFiled: November 20, 2020Publication date: March 11, 2021Applicant: Micron Technology, Inc.Inventors: Yangsung Joo, Hidekazu Noguchi