Patents by Inventor Hidekazu Noguchi

Hidekazu Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11356081
    Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: June 7, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hidekazu Noguchi
  • Publication number: 20220148646
    Abstract: Apparatuses and methods for calculating targeted refresh addresses may include circuitry that may be used to calculate victim row addresses having a variety of spatial relationships to an aggressor row. The spatial relationship of the victim row addresses calculated by the circuitry may be based, at least in part, on states of control signals provided to the circuitry. That is, the circuitry may be used to calculate the different victim row addresses by changing the states of the control signals.
    Type: Application
    Filed: November 9, 2020
    Publication date: May 12, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: HIDEKAZU NOGUCHI
  • Patent number: 11322192
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: May 3, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20220101910
    Abstract: Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same are disclosed. An example threshold voltage compensated sense amplifier according to the disclosure includes circuits, such as a first transistor having a first conductivity type coupled to a first node and a second node; a second transistor having a second conductivity type coupled to the first node and at third node; a plurality of transistors coupled to the second node and further configured to receive a power supply voltage; and a control circuit configured to provide a plurality of control signals to the plurality of transistors. The control circuit provides the plurality of control signals indicative of a first drive strength in a first memory operation and further provides the plurality of signals indicative of a second drive strength in a second memory operation.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Toshiyuki Sato, Hidekazu Noguchi
  • Publication number: 20220093165
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for controlling refresh operations. Responsive to a refresh command, or one or more pumps generated responsive to the refresh command, different banks of a memory array may perform different types of refresh operations for a pump. In some examples, the type of refresh operation performed by a bank may vary from pump to pump of a refresh operation.
    Type: Application
    Filed: September 23, 2020
    Publication date: March 24, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: SHINGO MITSUBORI, HIDEKAZU NOGUCHI
  • Patent number: 11257529
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: February 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Patent number: 11222686
    Abstract: Refresh commands may be provided at random intervals from a memory controller to a memory device. In some examples, refresh requests may be provided at random intervals which may be used to provide refresh commands from the memory controller to the memory device at random intervals. In some examples, an average time interval between refresh requests may be equal to a refresh interval of the memory device. In some examples, a maximum number of times the memory controller may postpone providing a refresh command to the memory device may be a random number. In some examples, a maximum value of the random number may be based, at least in part, on a minimum number of refresh commands required within a time interval by the memory device.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: January 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Hidekazu Noguchi
  • Publication number: 20210166752
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 3, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hidekazu Noguchi
  • Patent number: 10957377
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: March 23, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Hidekazu Noguchi
  • Publication number: 20210075408
    Abstract: Disclosed herein is an apparatus that includes a first circuit configured to generate a first signal a first number of times in response to an input signal, a second circuit configured to generate a second signal having a second numerical value each time the first signal is activated, and a third circuit configured to receive the second signal to update a count value obtained by accumulating the second numerical value, configured to generate a third signal each time the count value reaches a third numerical value, and configured to update the count value obtained by accumulating the second numerical value and subtracting the third numerical value when the count value reached the third numerical value.
    Type: Application
    Filed: September 6, 2019
    Publication date: March 11, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hidekazu Noguchi
  • Publication number: 20210074341
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the inning for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Application
    Filed: November 20, 2020
    Publication date: March 11, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Patent number: 10878862
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Publication number: 20200211632
    Abstract: Embodiments of the disclosure are drawn to apparatuses and methods for distributed timing of targeted refresh operations. Information stored in volatile memory cells may decay unless refresh operations are performed. A memory device may perform auto-refresh operations, as well as one or more types of targeted refresh operations, where particular rows are targeted for a refresh. Targeted refresh operations may draw less power than an auto-refresh operation. It may be desirable to distribute targeted refresh operations throughout a sequence of refresh operations, to average out a power draw in the memory device. Responsive to an activation of a refresh signal, the memory device may perform a group of refresh operations. At least one refresh operation in each group may be a targeted refresh operation.
    Type: Application
    Filed: December 26, 2018
    Publication date: July 2, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Hidekazu Noguchi
  • Publication number: 20200202921
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Application
    Filed: February 28, 2020
    Publication date: June 25, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20200090713
    Abstract: Apparatuses and methods for a temperature dependent delay between a wordline off signal and deactivating the wordline are disclosed. Memory devices may have reduced reliability when operating at relatively cold temperatures, which may be due in part to an increase in the write recovery time while the timing for a wordline to deactivate remains relatively unaffected. In some embodiments of the present disclosure, a delay circuit is used to insert a temperature dependent delay between a wordline off command being issued and the wordline being deactivated. The delay circuit may increase the length of temperature dependent delay at relatively cold temperatures, and decrease the length of the delay at relatively warm temperatures.
    Type: Application
    Filed: September 17, 2018
    Publication date: March 19, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Yangsung Joo, Hidekazu Noguchi
  • Patent number: 10580475
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: March 3, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20190228815
    Abstract: An example apparatus according to an aspect of the present disclosure includes an address scrambler circuit including a sub-wordline scrambler circuit configured to receive a first subset of bits of a row hammer hit address. The sub-wordline scrambler circuit is configured to perform a first set of logical operations on the first subset of bits to provide a second subset of bits, and to perform a second set of logical operations on the first subset of bits and the second subset of bits to provide a third subset of bits of an row hammer refresh address.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Masaru Morohashi, Hidekazu Noguchi
  • Publication number: 20150269988
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Applicant: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 9076503
    Abstract: A word driver drives a word line with a first power supply voltage and with a second power supply voltage which has a potential lower than the first power potential, respectively in a first time period and in a second time period following the first time period for activating the word line.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: July 7, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi
  • Patent number: 9053759
    Abstract: The semiconductor device includes a plurality of word lines classified into a plurality of groups and a selection circuit for selecting a word line according to an address. The selection circuit has a level shifter arranged for each of the groups. The address includes a first address for selecting any of the groups and a second address for selecting a word line in the selected group. The selection circuit selects a word line by allowing supply of active potential for word line by the level shifter of a group selected by the first address and further allowing supply of the active potential to the word line selected by the second address out of a plurality of word lines belonging to the selected group.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: June 9, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventor: Hidekazu Noguchi