Patents by Inventor Hidekazu Noguchi

Hidekazu Noguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020182800
    Abstract: The period of time required for a parallel test can be shortened by widening the application range of the parallel test. In the semiconductor memory device having a memory cell portions (5-A, 5-B), there are provided a column control means (1˜4) for simultaneously activating a plurality of columns which are subject to the degenerate substitution in the column redundant substitute; and a data read-out means (6-A, 6-B, SDBP-B0, SDBP-B1, and 9) for simultaneously reading out the data from a plurality of memory cells as selected by the above plurality of columns.
    Type: Application
    Filed: March 27, 2002
    Publication date: December 5, 2002
    Inventors: Koji Kuroki, Hidekazu Noguchi
  • Patent number: 6341086
    Abstract: A semiconductor memory circuit comprises a sense amplifier, a first data storing circuit for temporally storing and outputting the data from the sense amplifier in response to a latch signal and erasing the stored data in response to a first clear signal, a first determination circuit for determining whether the first data storing circuit stores the data and outputting a first determination signal representing the determination.
    Type: Grant
    Filed: January 26, 2001
    Date of Patent: January 22, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi
  • Publication number: 20010048633
    Abstract: A semiconductor memory circuit comprises a sense amplifier, a first data storing circuit for temporally storing and outputting the data from the sense amplifier in response to a latch signal and erasing the stored data in response to a first clear signal, a first determination circuit for determining whether the first data storing circuit stores the data and outputting a first determination signal representing the determination.
    Type: Application
    Filed: January 26, 2001
    Publication date: December 6, 2001
    Inventor: Hidekazu Noguchi
  • Patent number: 6218893
    Abstract: A power circuit includes an internal voltage regulation portion, a response time regulation portion, p-channel type field-effect transistors (FET) which serve as a voltage transformation portion, and a clock signal detection circuit. An external voltage input to the power circuit is transformed into an internal voltage which is set by a reference voltage, and the variance of the internal voltage may be compensated by the internal voltage regulation portion. Also, the response speed of the internal voltage regulation portion to the variance of the internal voltage may be regulated by the response time regulation portion. The clock signal detection portion detects a clock signal and switches an n-channel type FET in the response time regulation portion to an active state, thereby enhancing the response speed of the internal voltage regulation portion. Accordingly, the power circuit ensures stabilized output of power and effective power saving as well.
    Type: Grant
    Filed: October 7, 1998
    Date of Patent: April 17, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Hidekazu Noguchi