Patents by Inventor Hidekazu Oda
Hidekazu Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160315192Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.Type: ApplicationFiled: July 5, 2016Publication date: October 27, 2016Applicant: Renesas Electronics CorporationInventors: Hirokazu SAYAMA, Kazunobu OHTA, Hidekazu ODA, Kouhei SUGIHARA
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Patent number: 9443870Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.Type: GrantFiled: September 15, 2015Date of Patent: September 13, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
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Patent number: 9412867Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.Type: GrantFiled: November 5, 2015Date of Patent: August 9, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 9349816Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: GrantFiled: November 3, 2015Date of Patent: May 24, 2016Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20160087069Abstract: A semiconductor device includes an SOI substrate and a MISFET formed on the SOI substrate. The SOI substrate has a base substrate, a ground plane region formed on the base substrate, a BOX layer formed on the ground plane region and an SOI layer formed on the BOX layer. The base substrate is made of silicon and the ground plane region includes a semiconductor region made of silicon carbide.Type: ApplicationFiled: September 24, 2015Publication date: March 24, 2016Inventor: Hidekazu ODA
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Patent number: 9287259Abstract: MISFETs after the 32 nm technology node have a High-k gate insulating film and a metal gate electrode. Such MISFETs have the problem that the absolute value of the threshold voltage of n-MISFET and p-MISFET inevitably increases by the subsequent high temperature heat treatment. The threshold voltage is therefore controlled by forming various threshold voltage adjusting metal films on a High-k gate insulating film and introducing a film component from them into the High-k gate insulating film. The present inventors have however revealed that lanthanum or the like introduced into the High-k gate insulating film of the n-MISFET is likely to transfer to the STI region by the subsequent heat treatment. The semiconductor integrated circuit device according to the present invention is provided with an N channel threshold voltage adjusting element outward diffusion preventing region in the surface portion of the element isolation region below and at the periphery of the gate stack of the n-MISFET.Type: GrantFiled: April 9, 2012Date of Patent: March 15, 2016Assignee: Renesas Electronics CorporationInventors: Hirofumi Shinohara, Yukio Nishida, Katsuyuki Horita, Tomohiro Yamashita, Hidekazu Oda
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Publication number: 20160056254Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: ApplicationFiled: November 3, 2015Publication date: February 25, 2016Applicant: Renesas Electronics CorporationInventors: Kazunobu OTA, Hirokazu SAYAMA, Hidekazu ODA
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Publication number: 20160056289Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.Type: ApplicationFiled: November 5, 2015Publication date: February 25, 2016Applicant: Renesas Electronics CorporationInventors: Hirokazu SAYAMA, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Publication number: 20160005765Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.Type: ApplicationFiled: September 15, 2015Publication date: January 7, 2016Inventors: Hirofumi SHINOHARA, Hidekazu ODA, Toshiaki IWAMATSU
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Publication number: 20150364490Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.Type: ApplicationFiled: June 15, 2015Publication date: December 17, 2015Inventor: Hidekazu ODA
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Patent number: 9214464Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: GrantFiled: March 19, 2015Date of Patent: December 15, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
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Patent number: 9209191Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.Type: GrantFiled: July 8, 2014Date of Patent: December 8, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 9184053Abstract: An area in a top view of a region where a low-voltage field effect transistor is formed is reduced, and an area in a top view of a region where a high-voltage field effect transistor is formed is reduced. An active region where the low-voltage field effect transistors (first nMIS and first pMIS) are formed is constituted by a first convex portion of a semiconductor substrate that projects from a surface of an element isolation portion, and an active region where the high-voltage field effect transistors (second nMIS and second pMIS) are formed is constituted by a second convex portion of the semiconductor substrate that projects from the surface of the element isolation portion, and a trench portion formed in the semiconductor substrate.Type: GrantFiled: January 7, 2013Date of Patent: November 10, 2015Assignee: Renesas Electronics CorporationInventors: Hirofumi Shinohara, Hiromasa Yoshimori, Toshiaki Iwamatsu, Hidekazu Oda
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Patent number: 9166041Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.Type: GrantFiled: August 14, 2014Date of Patent: October 20, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
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Publication number: 20150194428Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: ApplicationFiled: March 19, 2015Publication date: July 9, 2015Applicant: Renesas Electronics CorporationInventors: Kazunobu OTA, Hirokazu SAYAMA, Hidekazu ODA
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Publication number: 20150137239Abstract: To suppress performance degradation of a semiconductor device, when the width of a first active region having a first field effect transistor formed therein is smaller than the width of a second active region having a second field effect transistor formed therein, the height of a surface of a first raised source layer of the first field effect transistor is made larger than the height of a surface of a second raised source layer of the second field effect transistor. Moreover, the height of a first surface of a raised drain layer of the first field effect transistor is made larger than a surface of a second raised drain layer of the second field effect transistor.Type: ApplicationFiled: August 27, 2014Publication date: May 21, 2015Inventors: Hirofumi Shinohara, Hidekazu Oda, Toshiaki Iwamatsu
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Patent number: 8987081Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: GrantFiled: September 9, 2014Date of Patent: March 24, 2015Assignee: Renesas Electronics CorporationInventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20150061006Abstract: In an SOI substrate having a semiconductor layer formed on the semiconductor substrate via an insulating layer, a MISFET is formed in each of the semiconductor layer in an nMIS formation region and a pMIS formation region. In power feeding regions, the semiconductor layer and the insulating layer are removed. In the semiconductor substrate, a p-type semiconductor region is formed so as to include the nMIS formation region and one of the power feeding regions, and an n-type semiconductor region is formed so as to include a pMIS formation region and the other one of the power feeding regions. In the semiconductor substrate, a p-type well having lower impurity concentration than the p-type semiconductor region is formed so as to contain the p-type semiconductor region, and an n-type well having lower impurity concentration than the n-type semiconductor region is formed so as to contain the n-type semiconductor region.Type: ApplicationFiled: August 14, 2014Publication date: March 5, 2015Inventors: Hirofumi SHINOHARA, Hidekazu ODA, Toshiaki IWAMATSU
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Publication number: 20140377920Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: ApplicationFiled: September 9, 2014Publication date: December 25, 2014Applicant: Renesas Electronics CorporationInventors: Kazunobu OTA, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20140322878Abstract: A gate insulating film and a gate electrode of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate. Using the gate electrode as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode is amorphized. Subsequently, a silicon oxide film is provided to cover the gate electrode, at a temperature which is less than the one at which recrystallization of the gate electrode occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode, and high tensile stress is applied to a channel region under the gate electrode. As a result, carrier mobility of the nMOS transistor is enhanced.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Applicant: Renesas Electronics CorporationInventors: Hirokazu SAYAMA, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara