Abstract: A semiconductor device which provides for reduction of a gate length and a resistance of a gate electrode of a MOS transistor, and a manufacturing method thereof, are provided. In forming a gate electrode (4), ions are implanted at a dose of 6×1015/cm2 or larger and annealing is performed, so that an upper portion of the gate electrode (4) expands. A silicide layer (4b) formed in the upper portion of the gate electrode (4) has a shape with an upper portion thereof being wider than a bottom portion thereof in section taken along a channel length direction. On the other hand, a polysilicon layer 4a has a shape with upper and bottom portions thereof having the substantially same width in section taken along a channel length direction, like the conventional structure. Thus, even when the width of the polysilicon layer (4a) is reduced to reduce a gate length, the width of the silicide layer (4b) is kept larger than the gate length, to prevent agglomeration of silicide in the silicide layer (4b).

Abstract: A semiconductor device capable of preventing variations in threshold voltage and having high reliability is provided. The semiconductor device includes a semiconductor substrate having a semiconductor region, and a field-effect transistor. The field-effect transistor includes a gate electrode, source and drain regions, and a channel region. The channel region includes a pair of lightly doped impurity regions having a relatively low impurity concentration as well as a heavily doped impurity region located between the lightly doped impurity regions and having a relatively high impurity concentration.

Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).

Abstract: Obtained are a semiconductor device which can prevent diffusion of an impurity contained in a gate electrode and a method of fabricating the same. In this semiconductor device, a gate oxide film and a P+-type gate electrode which are formed on a P-type silicon substrate are doped with nitrogen.

Abstract: This invention provides a MIS transistor with less electrical short between a gate and source/drain electrodes. A sidewall spacer 15 has a two-layer structure including a buffer layer 13 which consists of nitrided oxide silicon and a silicon nitrided layer 14 formed on the buffer layer 13. The sidewall spacer 15 serves as a mask to form a silicide film 10.

Abstract: A gate electrode is buried in a trench formed in the main surface of a semiconductor substrate and faces a counter doped layer, and source/drain layers are formed on both sides of the trench. Thus the source/drain layers are formed in shallower areas than the counter doped layer. As a result, the punch-through resistance is improved.

Abstract: A dopant is ion-implanted into a second region (52) of a polycrystalline silicon film (50) for a resistive element (5). Nitrogen or the like is ion-implanted into a second region (62) of a polycrystalline silicon film (60) for a resistive element (6). The density of crystal defects in the second regions (52, 62) is higher than that in first regions (51, 61). The density of crystal defects in a polycrystalline silicon film (70) for a resistive element (7) is higher near a silicide film (73). A polycrystalline silicon film (80) for a resistive element (8) is in contact with a substrate (2) with a silicide film in an opening of an isolation insulating film (3). The density of crystal defects in a substrate surface (2S) near the silicide film is higher than that in the vicinity. With such a structure, a current leak in an isolation region can be reduced.

Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor (100B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).

Abstract: A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.

Abstract: A MOSFET includes a silicon substrate (1) with trenches (2) formed therein. Each of the trenches (2) is completely filled with a silicon oxy-nitride (9) formed on inner wall faces (2W) and a bottom face (2B) thereof. The ratio between compositions of the silicon oxy-nitride (9) is controlled so that the silicon oxy-nitride (9) is approximately equal in thermal expansion coefficient to silicon. An end portion of the silicon oxy-nitride (9) along an opening of each trench (2) is located at a higher level than a main surface (1S) of the silicon substrate (1), and a surface of the silicon oxy-nitride (9) increases in height from the end portion toward the center thereof. The silicon oxy-nitride (9) has no depressions adjacent to the end portion thereof. Sidewall oxide films (41) and a gate electrode (5) are formed on a gate insulation film (4) formed in an active region.

Abstract: MOS type semiconductor device is formed on the primary surface of a semiconductor substrate. A channel region includes a punch-through stopper layer, a lower counter-doped layer, and an upper counter-doped layer. The punch-through stopper layer is formed between the source region and the drain region and has a first concentration peak. The lower counter-doped layer is formed between the source region and the drain region, and has a second concentration peak at a position shallower than the position of the first concentration peak. Further, the upper counter-doped layer is formed between the source region and the drain region, and has a third concentration peak at a position shallower than the position of the second concentration peak. A buried-channel semiconductor device exhibits high punch-through characteristics and prevents an increase in a threshold voltage.

Abstract: Provided are a semiconductor device in which a well is divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film (T) is formed such as to have to a depth (L1) from the main surface of a semiconductor substrate (100), and the area from the main surface of the substrate (100) to the depth (L1) is divided into a plurality of first regions (R1). A first well (W1) is formed in each of the first regions (R1). A second well (W2) is formed in a second region (R2) deeper than the first well (W1) in the substrate (100), and the second well (W2) is in contact with some of the first wells (W1).

Abstract: Grooves are formed in side walls to be adjacent to a gate electrode. Thereafter a silicide film is formed on a surface of the gate electrode. Thus, the gate electrode is prevented from electrical connection with a source/drain layer resulting from formation of silicide films on surfaces thereof, and its resistance value is prevented from being increased by the silicide films hardly causing phase transition following refinement.

Abstract: A semiconductor memory device and a method of manufacturing the same improves an efficiency of injection of channel hot electrons while suppressing injection of drain avalanche hot carriers. In the semiconductor memory device, a first nitrided oxide film (RNO film) containing a first content of hydrogen is formed at a drain avalanche hot carrier injection region. Thereby, injection of drain avalanche hot carriers is effectively suppressed during a data writing operation. A second nitrided oxide film (NO film) containing a second content of hydrogen larger than the first content is formed at a channel hot electron injection region. Thereby, an efficiency of injection of channel hot electrons is improved during the data writing operation.

Abstract: A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.

Abstract: There are provide a semiconductor device capable of increasing the operating speed of MOS transistors and improving current driving capability, and a method of manufacturing such a semiconductor device. A semiconductor device comprises a silicon substrate (1), an element isolation insulation film (2), a gate structure selectively formed on the main surface of the silicon substrate (1), and a sidewall (6) formed on the side face of the gate structure. The gate structure has a laminated structure with a gate insulation film (3) formed of a silicon oxide film, a gate electrode (4) formed of polysilicon, and a cobalt silicide layer (5) stacked in this order.

Abstract: Grooves are formed in side walls to be adjacent to a gate electrode. Thereafter a silicide film is formed on a surface of the gate electrode. Thus, the gate electrode is prevented from electrical connection with a source/drain layer resulting from formation of silicide films on surfaces thereof, and its resistance value is prevented from being increased by the silicide films hardly causing phase transition following refinement.

Abstract: Grooves are formed in side walls to be adjacent to a gate electrode. Thereafter a silicide film is formed on a surface of the gate electrode. Thus, the gate electrode is prevented from electrical connection with a source/drain layer resulting from formation of silicide films on surfaces thereof, and its resistance value is prevented from being increased by the silicide films hardly causing phase transition following refinement.