Patents by Inventor Hidekazu Oda
Hidekazu Oda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7470618Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.Type: GrantFiled: February 5, 2007Date of Patent: December 30, 2008Assignee: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Publication number: 20080308869Abstract: The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.Type: ApplicationFiled: August 20, 2008Publication date: December 18, 2008Applicant: Renesas Technology Corp.Inventors: Hidekazu ODA, Takahisa Eimori, Jiro Yugami, Takahiro Maruyama, Tomohiro Yamashita, Yukio Nishida, Shinichi Yamanari, Takashi Hayashi, Kenichi Mori
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Publication number: 20070207578Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: ApplicationFiled: May 1, 2007Publication date: September 6, 2007Applicant: Renesas Technology Corp.Inventors: Kazunobu OTA, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20070202634Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51-54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: ApplicationFiled: May 1, 2007Publication date: August 30, 2007Applicant: Renesas Technology Corp.Inventors: Kazunobu OTA, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20070128816Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.Type: ApplicationFiled: February 5, 2007Publication date: June 7, 2007Applicant: Renesas Technology Corp.Inventors: Hirokazu SAYAMA, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 7220637Abstract: A method of manufacturing a semiconductor device with NMOS and PMOS transistors is provided. The semiconductor device can lessen a short channel effect, can reduce gate-drain current leakage, and can reduce parasitic capacitance due to gate overlaps, thereby inhibiting a reduction in the operating speed of circuits. An N-type impurity such as arsenic is ion implanted to a relatively low concentration in the surface of a silicon substrate (1) in a low-voltage NMOS region (LNR) thereby to form extension layers (61). Then, a silicon oxide film (OX2) is formed to cover the whole surface of the silicon substrate (1). The silicon oxide film (OX2) on the side surfaces of gate electrodes (51–54) is used as an offset sidewall. Then, boron is ion implanted to a relatively low concentration in the surface of the silicon substrate (1) in a low-voltage PMOS region (LPR) thereby to form P-type impurity layers (621) later to be extension layers (62).Type: GrantFiled: August 6, 2002Date of Patent: May 22, 2007Assignee: Renesas Technology Corp.Inventors: Kazunobu Ota, Hirokazu Sayama, Hidekazu Oda
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Publication number: 20070111427Abstract: The semiconductor device which can apply the stress application technology to a channel part by a liner film to MISFET including a full silicidation gate electrode, and its manufacturing method are realized. The first liner silicon nitride film is formed on the semiconductor substrate MISFET formed. Insulating films, such as a silicon oxide film, are formed on the first liner silicon nitride film so that it may fully fill up the side of a gate electrode. Next, flattening processing is performed to an insulating film and the first liner silicon nitride film, and a polysilicon gate electrode is exposed. An insulating film is removed leaving the first liner silicon nitride film. The full silicidation of the exposed gate electrode is done, and the second liner silicon nitride film that covers the first liner silicon nitride film and the exposed full silicidation gate electrode is formed.Type: ApplicationFiled: November 15, 2006Publication date: May 17, 2007Inventors: Tomohiro Yamashita, Yukio Nishida, Hidekazu Oda
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Patent number: 7183204Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.Type: GrantFiled: May 12, 2005Date of Patent: February 27, 2007Assignee: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 7170109Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.Type: GrantFiled: June 10, 2004Date of Patent: January 30, 2007Assignee: Renesas Technology Corp.Inventors: Kohei Sugihara, Kazunobu Ota, Hidekazu Oda, Takahashi Hayashi
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Publication number: 20070007602Abstract: The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.Type: ApplicationFiled: July 3, 2006Publication date: January 11, 2007Applicant: Renesas Technology Corp.Inventors: Hidekazu Oda, Takahisa Eimori, Jiro Yugami, Takahiro Maruyama, Tomohiro Yamashita, Yukio Nishida, Shinichi Yamanari, Takashi Hayashi, Kenichi Mori
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Publication number: 20050202603Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an NMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the NMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the NMOS transistor is enhanced.Type: ApplicationFiled: May 12, 2005Publication date: September 15, 2005Applicant: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 6906393Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.Type: GrantFiled: July 17, 2003Date of Patent: June 14, 2005Assignee: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 6872642Abstract: A method of manufacturing a semiconductor device is provided which can suppress leakage current increases by making into silicide. Impurity that suppresses silicide formation reaction (suppression impurity), such as germanium, is introduced into source/drain regions (16, 36) from their upper surfaces. In the source/drain regions (16, 36), a region shallower than a region where the suppression impurity is distributed (50) is made into silicide, so that a silicide film (51) is formed in the source/drain regions (16, 36). Thus, by making the region shallower than the region (50) into silicide, it is possible to suppress that silicide formation reaction extends to the underside of the region to be made into silicide. This enables to reduce the junction leakage between the source/drain regions (16, 36) and a well region.Type: GrantFiled: May 21, 2003Date of Patent: March 29, 2005Assignee: Renesas Technology Corp.Inventors: Hidekazu Oda, Hirokazu Sayama, Kazunobu Ohta, Kouhei Sugihara
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Patent number: 6838747Abstract: A dopant is ion-implanted into a second region (52) of a polycrystalline silicon film (50) for a resistive element (5). Nitrogen or the like is ion-implanted into a second region (62) of a polycrystalline silicon film (60) for a resistive element (6). The density of crystal defects in the second regions (52, 62) is higher than that in first regions (51, 61). The density of crystal defects in a polycrystalline silicon film (70) for a resistive element (7) is higher near a silicide film (73). A polycrystalline silicon film (80) for a resistive element (8) is in contact with a substrate (2) with a silicide film in an opening of an isolation insulating film (3). The density of crystal defects in a substrate surface (2S) near the silicide film is higher than that in the vicinity. With such a structure, a current leak in an isolation region can be reduced.Type: GrantFiled: July 11, 2002Date of Patent: January 4, 2005Assignee: Renesas Technology Corp.Inventor: Hidekazu Oda
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Patent number: 6835610Abstract: A method of manufacturing a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a polysilicon layer on the gate insulating film, implanting ions into the polysilicon layer, patterning the polysilicon layer to form a gate electrode, annealing the gate electrode, and siliciding an upper portion of the gate electrode to form a silicide layer that has a lower portion facing the gate electrode and an upper portion opposite to the lower portion, the upper portion of the silicide layer being wider than the lower portion. A total dose of ions implanted during the step of implanting is 6×1015/cm2 or larger.Type: GrantFiled: June 3, 2003Date of Patent: December 28, 2004Assignee: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Publication number: 20040256634Abstract: A technique enabling to improve element isolation characteristic of a semiconductor device is provided. An element isolation structure is provided in a semiconductor substrate in which a silicon layer, a compound semiconductor layer and a semiconductor layer are laminated in this order. The element isolation structure is composed of a trench, a semiconductor film, and first and second insulating films. The trench extends through the semiconductor layer and extends to the inside of the compound semiconductor layer. The semiconductor film is provided on the surface of the trench, and the first insulating film is provided on the semiconductor film. The second insulting film is provided on the first insulating film and fills the trench.Type: ApplicationFiled: June 10, 2004Publication date: December 23, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Kohei Sugihara, Kazunobu Ota, Hidekazu Oda, Takashi Hayashi
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Publication number: 20040101999Abstract: A method of manufacturing a semiconductor device is provided which can suppress leakage current increases by making into silicide. Impurity that suppresses silicide formation reaction (suppression impurity), such as germanium, is introduced into source/drain regions (16, 36) from their upper surfaces. In the source/drain regions (16, 36), a region shallower than a region where the suppression impurity is distributed (50) is made into silicide, so that a silicide film (51) is formed in the source/drain regions (16, 36). Thus, by making the region shallower than the region (50) into silicide, it is possible to suppress that silicide formation reaction extends to the underside of the region to be made into silicide. This enables to reduce the junction leakage between the source/drain regions (16, 36) and a well region.Type: ApplicationFiled: May 21, 2003Publication date: May 27, 2004Applicant: Renesas Technology Corp.Inventors: Hidekazu Oda, Hirokazu Sayama, Kazunobu Ohta, Kouhei Sugihara
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Patent number: 6740939Abstract: CMOS transistors which can satisfy demand for size reduction and demand for reliability and a manufacturing method thereof are provided. A buried-channel type PMOS transistor is provided only in a CMOS transistor (100B) designed for high voltage; surface-channel type NMOS transistors are formed in a low-voltage NMOS region (LNR) and a high-voltage NMOS region (HNR), and a surface-channel type PMOS transistor is formed in a low-voltage PMOS region (LPR).Type: GrantFiled: March 19, 2002Date of Patent: May 25, 2004Assignee: Renesas Technology Corp.Inventors: Hirokazu Sayama, Yukio Nishida, Kazunobu Ohta, Hidekazu Oda
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Publication number: 20040097030Abstract: A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.Type: ApplicationFiled: July 17, 2003Publication date: May 20, 2004Applicant: Renesas Technology Corp.Inventors: Hirokazu Sayama, Kazunobu Ohta, Hidekazu Oda, Kouhei Sugihara
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Patent number: 6734523Abstract: A semiconductor device including a well divided into a plurality of parts by a trench, to effect a reduction in layout area, and a manufacturing method thereof. In the semiconductor device, an element isolation film is formed such as to have to a depth from the main surface of a semiconductor substrate, and the area from the main surface of the substrate to the depth is divided into a plurality of first regions. A first well is formed in each of the first regions. A second well is formed in a second region deeper than the first well in the substrate, and the second well is in contact with some of the first wells.Type: GrantFiled: September 14, 1999Date of Patent: May 11, 2004Assignee: Renesas Technology Corp.Inventors: Shuuichi Ueno, Tomohiro Yamashita, Hidekazu Oda