Patents by Inventor Hideki Endo

Hideki Endo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7876778
    Abstract: A packet transfer apparatus connects two networks of different protocols. The packet transfer apparatus, connected to a first communication network and a second communication network, performs the steps of: storing first destination correspondence information; receiving a packet of the first communication protocol; based on the first destination correspondence information, determining destination information of a packet of the second communication protocol corresponding to destination information of the received packet of the first communication protocol; generating the header of the packet of the second communication protocol, based on the determined destination information of the packet of the second communication protocol; converting the received one or more packets of the first communication protocol into one or more packets of the third communication protocol; and adding the generated header of the packet of the second communication protocol to the packets of the third communication protocol.
    Type: Grant
    Filed: March 12, 2008
    Date of Patent: January 25, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Takase, Hideki Endo, Takayuki Kanno, Akihiko Tanaka, Yoshihiro Ashi, Nobuyuki Yamamoto
  • Publication number: 20100313698
    Abstract: A pedal device includes a pedal suspended from a supporting shaft penetrating through a pair of lengthwise walls of a pedal bracket, and shaft detachment means configured to allow one end portion of the supporting shaft to be disengaged from a corresponding one of the lengthwise walls at the time of forward collision. A pedal stroke sensor is arranged on the pedal bracket at a distance from the pedal, and the pedal stroke sensor and the pedal are connected to each other by a transmission mechanism. The transmission mechanism includes permission means for permitting the end portion of the supporting shaft to be disengaged from the corresponding lengthwise wall at the time of forward collision.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 16, 2010
    Inventors: Shuichi Yoshida, Hideki Endo
  • Publication number: 20100313699
    Abstract: A pedal stroke sensor is placed at a point of a pedal bracket, which is located away from a pedal, and where the pivot of the pedal stroke sensor is not aligned with the pivot of the pedal; the pedal and the pedal stroke sensor, which are thus separated away from each other, are connected together by a link mechanism; and a pedal deflection is transmitted through the link mechanism to the pedal stroke sensor.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 16, 2010
    Inventors: Shuichi YOSHIDA, Hideki Endo
  • Publication number: 20100290933
    Abstract: An electric pump includes a pump; a motor having a motor shaft, the motor shaft being connected to the pump to drive the pump; a support member which is arranged between the pump and a front end portion of the motor, the front end portion of the motor being a motor shaft side, the support member supporting the pump and the motor when the motor shaft penetrates the pump; a motor cover which covers the motor, the motor cover having a closed-end cylindrical shape, and an opened end side of the motor cover being fixed to the support member; and an elastic member which is in a state of being compressed positioned between a rear end portion of the motor and a bottom portion of the motor cover. The motor is supported by the support member as being urged thereto by the elastic member.
    Type: Application
    Filed: May 14, 2010
    Publication date: November 18, 2010
    Applicants: MIKUNI CORPORATION, MITSUBUSHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Shingo Tabata, Michihiro Yokoyama, Minoru Suzuki, Yoshihiro Sakaguchi, Hideki Endo, Haruo Kotera, Naohisa Koike, Kenta Tanaka
  • Patent number: 7830895
    Abstract: A packet communication apparatus comprising a node management processor for controlling the whole apparatus, network interfaces for transmitting and receiving packets to and from external networks, function enhancement modules for performing predetermined processes on the packets, and a switch for transferring the packets within the apparatus. The network interface includes a CPU and a memory, the memory stores a program executed by the CPU, the CPU processes the packet received from the external networks by executing the program, and the function enhancement module stores the program stored in the memory.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: November 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hideki Endo, Kunihiko Toumura, Toshiaki Suzuki
  • Publication number: 20100226244
    Abstract: Provided is a multicast path management method for a connectionless communication. Also provided is a path protection function which is effective when a path has failed. A network is formed by a trunk and a branch path. The multicast path is managed by end-to-end and when a failure has occurred, an instruction is issued from the apex of the multicast tree to respective end-to-end paths so as to switch from the currently used channel to a backup path. Thus, upon failure, an individual path protection can be performed without affecting other parts of the tree to which the same multicast flow as the defective path is distributed or the distribution state of the multicast flow.
    Type: Application
    Filed: August 4, 2006
    Publication date: September 9, 2010
    Applicant: HITACHI COMMUNICATION TECHNOLOGIES, LTD.
    Inventors: Masahiko Mizutani, Atsushi Iwamura, Yoshihiro Ashi, Masayuki Takase, Hideki Endo
  • Publication number: 20100220743
    Abstract: A packet communication apparatus includes a frame buffer of a linked list method and holds chain information and buffer size information, for structuring a linked list buffer for each user flow, in two areas consisting of an operation area and an update area. While usually in service, the buffer is structured by using the chain information in the operation area and the buffer size information in the same area such that the frame is read/written in the frame buffer. When the chain information in the update area and the buffer size information in the same area have been changed, a queue size is changed by reflecting the updated chain information and the updater buffer size information into the operation area, when both the read pointer and the write pointer respectively have gone around the buffer, or when there is no frame stored in the buffer.
    Type: Application
    Filed: February 3, 2010
    Publication date: September 2, 2010
    Applicant: HITACHI, LTD.
    Inventors: Hideki ENDO, Akihiko TANAKA, Takayuki KANNO, Masayuki TAKASE, Taisuke UETA
  • Publication number: 20100150554
    Abstract: A PON system capable of utilizing the bandwidth of an optical transmission channel in the PON section. In a PON system including an OLT and a plurality of ONUs, the OLT has: a downstream frame processing unit that removes at least part of the header information in a layer 2 header from a downstream frame received from a wide area network, and converts the remaining frame portion into a frame having a header specific to the PON section; and a downstream frame processing unit that extracts a downstream frame portion to be transferred to a user terminal, from a received frame from a PON, and adds the layer 2 header information deleted in the OLT.
    Type: Application
    Filed: February 16, 2010
    Publication date: June 17, 2010
    Inventors: Masahiko Mizutani, Takeshi Shibata, Tohru Kazawa, Yoshihiro Ashi, Masanobu Kobayashi, Hideki Endo
  • Publication number: 20100135162
    Abstract: A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.
    Type: Application
    Filed: February 3, 2010
    Publication date: June 3, 2010
    Applicant: HITACHI, LTD.
    Inventors: Masayuki Takase, Hideki Endo, Takayuki Kanno, Nobuyuki Yamamoto
  • Patent number: 7675936
    Abstract: A PON system capable of utilizing the bandwidth of an optical transmission channel in the PON section. In a PON system including an OLT and a plurality of ONUs, the OLT has: a downstream frame processing unit that removes at least part of the header information in a layer 2 header from a downstream frame received from a wide area network, and converts the remaining frame portion into a frame having a header specific to the PON section; and a downstream frame processing unit that extracts a downstream frame portion to be transferred to a user terminal, from a received frame from a PON, and adds the layer 2 header information deleted in the OLT.
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: March 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masahiko Mizutani, Takeshi Shibata, Tohru Kazawa, Yoshihiro Ashi, Masanobu Kobayashi, Hideki Endo
  • Patent number: 7675859
    Abstract: A link aggregation function and maintenance function by MPLS OAM. Identical entry information is stored in plural circuits IF which perform a LA setting. In this way, multiplexing to the same LSP is possible even with different IF. The first network IF is assumed to be OAM ACT, and the second network IF is set to OAM SBY (SBY). OAM frame insertion is performed only by an OAM ACT port. In this way, in an opposite MPLS transmission apparatus, it is possible to prevent CV frame reception above a specified number of frames. Further, a switch forwarding table is set to forward frames from the network side to the first network IF of OAM ACT. The second network IF which was set to OAM SBY does not perform fault detection by CV reception. In this way, incorrect detection of faults due to non-reception of OAM can be prevented.
    Type: Grant
    Filed: August 20, 2007
    Date of Patent: March 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Takase, Hideki Endo, Takayuki Kanno, Nobuyuki Yamamoto
  • Publication number: 20100021161
    Abstract: Disclosed herewith is a PON system and a bandwidth controlling method capable of controlling congestion with use of an upstream bandwidth in a PON section efficiently when congestion occurs in a gateway (GW) connected to an OLT. An OLT connected to a plurality of ONUs through a passive optical network (PON) and to a gateway (GW) through a communication line, when receiving a congestion occurrence notice indicating a congestion occurred output number from a GW, identifies the identifier of the ONU that is using a GW output line having the congestion output port number and shifts the bandwidth controlling of the PON section in a normal mode for allocating a bandwidth to each ONU normally to that in a bandwidth suppression mode for allocating a congestion time allowable bandwidth that is less than the current bandwidth to the ONU having the identified ONU identifier and a bandwidth to each of other ONUs according to its transmission queue length.
    Type: Application
    Filed: October 2, 2009
    Publication date: January 28, 2010
    Applicant: HITACHI COMMUNICATION TECHNOLOGIES, LTD.
    Inventors: Hideki Endo, Masahiko Mizutani, Masayuki Takase, Kenichi Sakamoto, Yoshihiro Ashi, Takayuki Kanno, Nobuyuki YAMAMOTO
  • Publication number: 20090303996
    Abstract: Provided is a network system including a start device and multiple end devices. A point-to-point (P-to-P) logical path is set to be used for unicast communication between the start device and each of the end devices. A first point-to-multipoint (P-to-M) logical path and a second P-to-M logical path are set to be used for multicast communication from the start device to the multiple end devices. The start device transmits data over the first P-to-M logical path. When one of the end devices detects a defect along the first P-to-M logical path, the end device that has detected the defect transmits a switch request over the P-to-P logical path set between this end device and the start device. The start device receives the switch request and transmits data over the second P-to-M logical path.
    Type: Application
    Filed: June 5, 2009
    Publication date: December 10, 2009
    Applicant: HITACHI COMMUNICATION TECHNOLOGIES, LTD.
    Inventors: Masayuki TAKASE, Hideki ENDO, Taisuke UETA, Takayuki KANNO
  • Patent number: 7602800
    Abstract: Disclosed herewith is a PON system and a bandwidth controlling method capable of controlling congestion with use of an upstream bandwidth in a PON section efficiently when congestion occurs in a gateway (GW) connected to an OLT. An OLT connected to a plurality of ONUs through a passive optical network (PON) and to a gateway (GW) through a communication line, when receiving a congestion occurrence notice indicating a congestion occurred output number from a GW, identifies the identifier of the ONU that is using a GW output line having the congestion output port number and shifts the bandwidth controlling of the PON section in a normal mode for allocating a bandwidth to each ONU normally to that in a bandwidth suppression mode for allocating a congestion time allowable bandwidth that is less than the current bandwidth to the ONU having the identified ONU identifier and a bandwidth to each of other ONUs according to its transmission queue length.
    Type: Grant
    Filed: February 5, 2007
    Date of Patent: October 13, 2009
    Assignee: Hitachi Communication Technologies, Ltd.
    Inventors: Hideki Endo, Masahiko Mizutani, Masayuki Takase, Kenichi Sakamoto, Yoshihiro Ashi, Takayuki Kanno, Nobuyuki Yamamoto
  • Publication number: 20090232148
    Abstract: A packet communication system of this invention includes a user access device at a user point for providing a user with connectivity to a plurality of carriers, carrier communication networks linked to the user access device, and a carrier management network which controls and manages the user access device and communication devices. A communication device receives a control frame-inserting command from the carrier management network, and sends a control frame containing therein control frame transfer information that indicates which one of termination and send-back processing is performed at a destination device. In response to receipt of the control frame, a user access device that is the destination of this frame extracts therefrom the control frame transfer information. If this information indicates the termination then perform termination; if send-back, add thereto a header necessary for the send-back and then transfer it.
    Type: Application
    Filed: February 20, 2009
    Publication date: September 17, 2009
    Inventors: Hideki ENDO, Masayuki Takase, Takayuki Kanno, Akihiko Tanaka
  • Publication number: 20090232265
    Abstract: A clock data recovery circuit that supplies stable reproduction clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2?. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reproduction clock.
    Type: Application
    Filed: January 27, 2009
    Publication date: September 17, 2009
    Inventors: Masayuki Takase, Hideki Endo, Koji Fukuda, Kenichi Sakamoto
  • Patent number: D595669
    Type: Grant
    Filed: April 10, 2008
    Date of Patent: July 7, 2009
    Assignee: Alpine Electronics, Inc.
    Inventors: Hideki Endo, Takayuki Horie
  • Patent number: D608774
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: January 26, 2010
    Assignee: Alpine Electronics, Inc.
    Inventors: Taro Iwamoto, Hideki Endo
  • Patent number: D634729
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: March 22, 2011
    Assignee: Alpine Electronics, Inc.
    Inventors: Hideki Endo, Hiroshi Fujimoto
  • Patent number: D635970
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: April 12, 2011
    Assignee: Alpine Electronics, Inc.
    Inventors: Takashi Ichikawa, Hideki Endo, Taro Iwamoto, Mitsuhiro Yashiro, Makoto Nishiyama