Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.

Abstract: The invention relates to a low-cost transfer bump sheet which is capable of transferring copper-cored solder bumps with high reliability of bonding to a semiconductor chip and which is capable of transferring bumps of various structures. The invention also relates to a low-cost semiconductor flip chip in which copper-cored solder bumps with high reliability of bonding are mounted on a semiconductor chip through the use of the transfer bump sheet. In the transfer bump sheet, metal posts of two or more layers are formed on a base sheet.

Abstract: The present invention provides a method of forming a diffusion layer which extends on bottoms and side walls of trench grooves as well as on top portions of ridged portions separating the trench grooves, and the trench grooves being separated by ridged portions of the substrate so that the trench grooves and the ridged portions are aligned between adjacent two of gate electrode structures, the method comprising the steps of: carrying out a first ion-implantation in a vertical direction to introduce an impurity into the bottoms of the trench grooves and into top portions of the ridged portions by use of gate electrode structures; forming side wall insulation films on side wails of the gate electrode structures; and carrying out a second ion-implantation in an oblique direction with a rotation of the substrate by use of the gate electrode structures and the side walls.

Abstract: An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the image data into frame image data and to store the frame image data in a respective local frame buffer; a control processor operable to provide instructions to the plurality of graphics processors; and at least one merge unit operable to synchronously receive the frame image data from the respective local frame buffers and to synchronously produce combined frame image data based thereon

Abstract: There is provided a storage method of a semiconductor storage apparatus provided with a source/drain area formed in a semiconductor substrate, a floating gate formed on a top layer of the area via a gate insulating film, and a control gate formed on the floating gate via an interlayer insulating film, the method comprising steps of: applying a predetermined positive voltage to a bit line connected to the drain area and a word line connected to the control gate, injecting an electron to the floating gate, and writing data to a selected memory cell; applying a predetermined negative voltage to a gate line, applying the predetermined positive voltage to a common source line connected to the semiconductor substrate or the source area, discharging the electron accumulated in the floating gate of the selected memory cell, and performing data erasing; and after the data erasing, applying the predetermined positive voltage necessary for injecting the electron to the floating gate from a channel area in the vicinity o

Abstract: The present invention provides a network apparatus for a network of ring topology configuration in which an insertion of an I/O card automatically ring-connects the I/O card and a removal of the I/O card automatically leaves the empty position ring-connected. A connector 1 which is ring-connected to a network includes connection means to be inserted to intervene a signal line. The connection means has a first terminal member and a second connection member. In a first state of the connection means, the first terminal member is in contact with the second terminal member so as to establish an electrical connection between the first terminal member and the second terminal member.

Abstract: A semiconductor device includes a field oxide film, a plurality of word lines, an insulating interlayer film, a plurality of contact holes, a plurality of protective diffusion layers, a plurality of common contact holes, and a plurality of metal plugs. The field oxide film is formed on a silicon substrate having one conductivity type. The word lines are formed by patterning on the field oxide film. The insulating interlayer film is formed on the field oxide film to cover the word lines. The contact holes are formed in the field oxide film to be self-aligned with the word lines. The protective diffusion layers have an opposite conductivity type and are formed on a surface of the semiconductor substrate to correspond to the contact holes. The common contact holes are formed in the insulating interlayer film to extend across the word lines and the protective diffusion layers. The common contact holes are formed at a depth to reach the protective diffusion layers while partly exposing the word lines.

Abstract: In a data erase operation of the present invention, a drain terminal is opened. A negative voltage of about -10 V and a voltage of about 5 V are applied to a cell gate and a source terminal, respectively. The voltage of about 1-2 V is applied to a P well terminal and an N well terminal. A ground potential is provided to a substrate. A voltage which is lower than the voltage of the source terminal and higher than the substrate voltage (ground voltage) is applied to a P well and an N well between a source diffusion layer and the substrate. Thus, an electric field generated between a source and a floating gate realizes the erase by means of F-N tunneling.

Abstract: A semiconductor device includes a field oxide film, a plurality of word lines, an insulating interlayer film, a plurality of contact holes, a plurality of protective diffusion layers, a plurality of common contact holes, and a plurality of metal plugs. The field oxide film is formed on a silicon substrate having one conductivity type. The word lines are formed by patterning on the field oxide film. The insulating interlayer film is formed on the field oxide film to cover the word lines. The contact holes are formed in the field oxide film to be self-aligned with the word lines. The protective diffusion layers have an opposite conductivity type and are formed on a surface of the semiconductor substrate to correspond to the contact holes. The common contact holes are formed in the insulating interlayer film to extend across the word lines and the protective diffusion layers. The common contact holes are formed at a depth to reach the protective diffusion layers while partly exposing the word lines.

Abstract: The semiconductor memory device includes a first conductivity type semiconductor substrate, a tunnel gate oxide film formed on the semiconductor substrate, a floating gate formed on the tunnel gate oxide film, and a control gate formed on the floating gate. The semiconductor substrate includes second conductivity type source and drain regions, a second conductivity type lightly doped region formed so that it covers the source region, and a first conductivity type heavily doped region formed so that it covers at least the drain region and overlaps at least partially with the lightly doped region beneath the floating ate. The semiconductor memory device prevents excessive data erasure regardless of the dispersion in thickness of the tunnel gate oxide film, thereby preventing misreading and enhancing reliability of operation.

Abstract: A floating gate type field effect transistor increases the threshold during an application of a write-in pulse to the control gate electrode thereof so as to inject hot electrons into the floating gate electrode, and the write-in pulse is decayed along a waveform having a gradient smaller than a gradient of a pulse signal assumed to take place in a source/drain region of a non-selected floating gate type field effect transistor sharing the selected word line with the selected floating gate type field effect transistor, thereby preventing the non-selected floating gate type field effect transistor from the gate disturb phenomenon.

Abstract: Gate insulating film of a memory cell in a nonvolatile semiconductor memory devices is protected from a plasma damage by a residual side wall insulating film. After forming field oxide films and first gate insulating films, gate structures each including a control gate, a second insulating film and a floating gate is formed. A fourth insulating films are deposited on the entire surface and ion-etched to leave residual side wall insulating films at the side walls of each of the gate structures. The residual side wall films protect the first gate insulating films and silicon substrate from a plasma damage. At least one of the source and drain is formed in a LDD structure due to the ion-implantation through the residual side wall insulating films. Resistance characteristics to breakdown due to a high voltage can be improved by reducing deterioration of the first gate insulating films. Other electric characteristics can be improved by the LDD structure.

Abstract: A fabrication method of a split-gate type flash EEPROM with an improved data-storage characteristic. Insulator strips extending along a first direction are formed on a semiconductor substrate at intervals. The strips are in contact with active regions and a field insulator film. After a first gate insulator film is formed on uncovered parts of the active regions, respectively, a first patterned conductor film is formed to cover the insulator strips and the first gate insulator film. The first conductor film is anisotropically etched to produce floating gate electrodes lower in height than the stripes on the first gate insulator film without using a mask. Each of the floating gate electrodes has an oblique side face. A second gate insulator film is formed to cover the floating gate electrodes and exposed parts of the active regions. A second conductor film is formed to cover the second gate insulator film and the insulator strips.

Abstract: A plastic sealed semiconductor device designed to prevent sliding of wiring due to thermal stress is disclosed. A lower layer wiring is provided adjacent to an outside of a portion of an uppermost layer of wiring covered by a cover film, which is arranged closest to an outer periphery of the semiconductor chip. Compressive stress of the sealing resin is divided by a step portion due to the uppermost layer of wiring and a step portion due to the lower layer of wiring. Further, since the interlayer insulating film covering the lower layer of wiring is flattened, the step portions are inclined gently in which stress is further divided. Therefore, the sliding of wiring is reliably prevented.

Abstract: A semiconductor memory device comprises a plurality of word lines (WL1, WL2), a plurality of bit lines (BL1, BL"), a plurality of memory cells (MC11, MC12) each includes a transistor (9) formed on a first semiconductor region (3) and having a floating gate (6), a control gate (8) connected to one of said word lines, a source region (5s) and a drain region (5d) connected to a first end of one of said bit lines, and further comprises a source line (SL) having a first capacitance thereof different from a second capacitance which is associated with said bit lines (BL1, BL2) and having a first end thereof connected to said source region, a first bias means (14) for charging said bit lins and said source line via said first semicondictor region to a high voltage level (Vcc) during a first time period and supplying a low voltage level (Vss) to said first semiconductor region during a second time period thereafter, wherein said low voltage level causes a voltage difference and a current between said source and drain

Abstract: A process for preparing a polyamide is provided. The polyamide is prepared by causing a dicarboxylic acid and a diamine to polycondensate directly under an atmosphere of an inert gas at atmospheric pressure. The polycondensation reaction is mainly carried out in two diamine component-adding steps, one step comprising adding part of the diamine to the molten dicarboxylic acid until the molar ratio of the diamine to the dicarboxylic acid is brought to within the range of from 0.900 to 0.990 while raising continuously the temperature of the reaction mixture to a temperature not exceeding about 5.degree. C. above the melting point of the object polyamide and the other step comprising adding the remainder of the diamine to the reaction mixture maintained at a temperature higher than about 10.degree. C., but not exceeding about 35.degree. C. above the melting point of the object polyamide until the overall molar ratio of the diamine to the dicarboxylic acid is brought to within the range of from 0.995 to 1.005.

Abstract: A solid carrier for catalytic material is coated with a slurry composed of alumina hydrate (Al.sub.2 O.sub.3.nH.sub. 2 O) dried at 250.degree..about.350.degree.C, colloidal silica and water. Said carrier, after drying, is immersed in an aqueous solution of aluminum nitrate (Al(NO.sub.3).sub.3) containing a nitrate of barium, lanthanum or another rare earth element and then dried and fired.