Patents by Inventor Hideki Hara

Hideki Hara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110308848
    Abstract: Disclosed are a composite body, a method for producing the composite body and a semiconductor device, the composite body comprising a resin layer and a fine wiring and/or via hole being formed in the resin layer, having high adhesion and high reliability, and being capable of high frequencies. Also disclosed are a resin composition and a resin sheet, both of which can provide such a composite body. The composite body comprises a resin layer and an electroconductive layer, wherein a groove having a maximum width of 1 ?m or more and 10 ?m or less is on a surface of the resin layer; the electroconductive layer is inside the groove; and a surface of the resin layer being in contact with the electroconductive layer has an arithmetic average roughness (Ra) of 0.05 ?m or more and 0.
    Type: Application
    Filed: February 8, 2010
    Publication date: December 22, 2011
    Applicant: SUMITOMO BAKELITE COMPANY, LTD.
    Inventors: Yuka Ito, Kenichi Kaneda, Yasuaki Mitsui, Iji Onozuka, Noriyuki Ohigashi, Hideki Hara
  • Publication number: 20110084409
    Abstract: A semiconductor element mounting board includes: a board having surfaces; a semiconductor element provided at a side of one of the surfaces of the board; a bonding agent layer through which the board and the semiconductor element are bonded together, the bonding agent layer having a storage modulus at 25° C. of 5 to 1,000 MPa; a first layer into which the semiconductor element is embedded, the first layer provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer.
    Type: Application
    Filed: June 3, 2009
    Publication date: April 14, 2011
    Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
  • Publication number: 20110011124
    Abstract: A refrigeration apparatus (20) includes a refrigerant circuit (10) in which refrigerant is circulated by a compressor (30) to perform a refrigeration cycle. The compressor (30) includes a fluid machine (82) for compressing refrigerant; and an electric motor (85) for driving the fluid machine (82). Refrigerant oil having volume resistivity of equal to or greater than 1010 ?·m at 20° C. is used for the compressor (30).
    Type: Application
    Filed: March 18, 2009
    Publication date: January 20, 2011
    Inventors: Hideki Matsuura, Masaru Tanaka, Hideki Hara
  • Publication number: 20110011123
    Abstract: In a refrigeration apparatus including a refrigerant circuit in which refrigerant represented by Molecular Formula 1: C3HmFn (note that “m” and “n” are integers equal to or greater than 1 and equal to or less than 5, and a relationship represented by an expression m+n=6 is satisfied) and having a single double bond in a molecular structure, or refrigerant mixture containing the refrigerant is used, predetermined functional resin components arranged so as to contact refrigerant of the refrigerant circuit are made of any of polytetrafluoroethylene, polyphenylene sulfide, phenolic resin, polyamide resin, chloroprene rubber, silicone rubber, hydrogenated nitrile rubber, fluorine-containing rubber, and hydrin rubber.
    Type: Application
    Filed: March 5, 2009
    Publication date: January 20, 2011
    Inventors: Hideki Matsuura, Masaru Tanaka, Hideki Hara, Kouji Shibaike, Youichi Ohnuma
  • Publication number: 20100326129
    Abstract: The whole of a refrigerant circuit in which a refrigeration cycle is performed is accommodated in a casing. A heat medium circuit is provided, which is connected to the refrigerant circuit through a utilization-side heat exchanger, and which supplies a heat medium exchanging heat with refrigerant in the heat exchanger, to a predetermined heat utilization target. As the refrigerant of the refrigerant circuit, refrigerant which is represented by a molecular formula C3HmFn (note that “m” and “n” are integers equal to or greater than 1 and equal to or less than 5, and a relationship represented by an expression m+n=6 is satisfied), and which has a single double bond in a molecular structure, or refrigerant mixture containing such refrigerant is used.
    Type: Application
    Filed: February 24, 2009
    Publication date: December 30, 2010
    Inventors: Michio Moriwaki, Hideki Hara, Syuji Furui
  • Publication number: 20100319377
    Abstract: In a refrigeration apparatus (20), refrigerant mixture in which the C3HmFn refrigerant represented by Molecular Formula 1: C3HmFn (note that “m” and “n” are integers equal to or greater than 1 and equal to or less than 5, and a relationship represented by an expression m+n=6 is satisfied) and having a single double bond in a molecular structure is equal to or greater than 70% by mass and equal to or less than 94% by mass, and the proportion of HFC refrigerant is equal to or greater than 6% by mass and equal to or less than 30% by mass; refrigerant mixture containing the C3HmFn refrigerant and particular refrigerant such as hydrocarbons; or refrigerant mixture containing 2,3,3,3-tetrafluoro-1-propene and carbon dioxide is used.
    Type: Application
    Filed: March 3, 2009
    Publication date: December 23, 2010
    Inventors: Michio Moriwaki, Hideki Hara, Shuji Furui
  • Publication number: 20100254421
    Abstract: Within a semiconductor laser device, mounting a semiconductor laser element array of multi-beam structure on a sub-mount, the semiconductor laser element array of multi-beam structure comprises one piece of a semiconductor substrate 11; a common electrode 1, which is formed on a first surface of the semiconductor substrate; a semiconductor layer 2, which is formed on the other surface of the semiconductor substrate, and has a plural number of light emitting portions 7 within an inside thereof; a plural number of anode electrodes 3 of a second conductivity type, which are formed above the plural number of light emitting portions, respectively; and a supporting portion 25, which is provided outside a region of forming the light emitting portions, wherein on one surface of the sub-mount is connected an electrode 3 of the semiconductor laser element array through a solder 4, and that solder 4 is formed to cover a supporting portion and an electrode neighboring thereto, and further on the electrode 3 is formed a g
    Type: Application
    Filed: March 31, 2010
    Publication date: October 7, 2010
    Inventors: Yoshihiko IGA, Hiroshi MORIYA, Yutaka INOUE, Hideki HARA, Keiichi MIYAUCHI
  • Publication number: 20100213597
    Abstract: A semiconductor element mounting board includes: aboard having surfaces; a semiconductor element mounted on one of the surfaces of the board; a first layer into which the semiconductor element is embedded, the first layer being provided on the one surface of the board; a second layer provided on the other surface of the board, the second layer being constituted from the same material as that of the first layer, the constituent material of the second layer having the same composition ratio as that of the constituent material of the first layer; and surface layers provided on the first and second layers, respectively, each of the surface layers being formed from at least a single layer. In such a semiconductor element mounting board, each of the surface layers has rigidity higher than that of each of the first and second layers. It is preferred that in the case where a Young's modulus of each surface layer at 25° C. is defined as X GPa and a Young's modulus of the first layer at 25° C.
    Type: Application
    Filed: October 15, 2008
    Publication date: August 26, 2010
    Applicant: SUMITOMO BAKELITE COMPANY LIMITED
    Inventors: Mitsuo Sugino, Hideki Hara, Toru Meura
  • Patent number: 7746910
    Abstract: A semiconductor laser diode device with small driving current and no distortion in the projected image.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: June 29, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Satoshi Kawanaka, Atsushi Nakamura, Masato Hagimoto, Hideki Hara, Masakatsu Yamamoto
  • Patent number: 7640388
    Abstract: A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: December 29, 2009
    Assignee: Sony Corporation
    Inventors: Katsuya Nakashima, Hideki Hara, Takashi Akai, Toshifumi Nomura, Kazumi Sato, Yukihisa Tsuneda, Toshiyuki Nishihara
  • Publication number: 20090293803
    Abstract: By providing a length of not less than 100 mm to a tail portion to be formed following the cylindrical body portion in growing silicon single crystals having a cylindrical body portion with a diameter of 450 mm using the CZ method, it becomes possible to inhibit the occurrence of dislocations in the tail portion and thus achieve improvements in yield and productivity. A transverse magnetic field having an intensity of not less than 0.1 T is preferably applied on the occasion of formation of that tail portion.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 3, 2009
    Inventors: Takanori Tsurumaru, Hideki Hara, Ryoichi Kaito
  • Publication number: 20090293804
    Abstract: A method of shoulder formation in growing silicon single crystals by the CZ method which comprises causing the taper angle to vary in at least two stages, desirably three stages or four stages, can inhibit the occurrence of dislocations in the shoulder formation step and thereby improve the yield and increase the productivity. As the number of stages resulting from varying the taper angle is increased, possible disturbances to occur at crystal growth interfaces and incur dislocations can be reduced and, further, when the above shoulder formation method is applied under application of a transverse magnetic field having a predetermined intensity, the occurrence of dislocations can be inhibited and defect-free silicon single crystals suited for the manufacture of wafers can be grown with high production efficiency. Therefore, the method is best suited for the production of large-diameter silicon single crystals with a diameter of 450 mm which are to be applied to manufacturing semiconductor devices.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 3, 2009
    Inventors: Hiroaki Taguchi, Hideki Hara, Ryoichi Kaito
  • Publication number: 20090293802
    Abstract: By giving a shoulder portion height of at least 100 mm in growing silicon single crystals having a diameter of 450 mm (weighing up to 1100 kg) by the CZ method, it becomes possible to inhibit the occurrence of dislocations in the shoulder formation step to thereby achieve a yield improvement and increase productivity. Furthermore, when this method is applied under application of a transverse magnetic field with a predetermined intensity, the occurrence of dislocations can be further inhibited and, accordingly, defect-free silicon single crystals suited for wafer manufacture can be grown with high production efficiency. Thus, the method is best suited for the production of large-diameter silicon single crystals having a diameter of 450 mm, which are applied in the manufacture of semiconductor devices.
    Type: Application
    Filed: June 1, 2009
    Publication date: December 3, 2009
    Inventors: Hiroaki Taguchi, Hideki Hara, Ryoichi Kaito
  • Publication number: 20080181276
    Abstract: A semiconductor laser diode device with small driving current and no distortion in the projected image.
    Type: Application
    Filed: January 31, 2008
    Publication date: July 31, 2008
    Inventors: Satoshi Kawanaka, Atsushi Nakamura, Masato Hagimoto, Hideki Hara, Masakatsu Yamamoto
  • Publication number: 20070296021
    Abstract: A manufacturing method of a nonvolatile semiconductor memory includes steps (a) to (d). The (a) is a step of laminating a 2nd insulating film, a gate film and a hard mask film which cover a 1st gate electrode of a 1st memory cell transistor formed on a 1st region of a semiconductor substrate through a 1st insulating layer and a 3rd gate electrode of a 2nd memory cell transistor formed on a 2nd region through the 1st insulating layer. The (b) is a step of forming a 1st hard mask layer which covers a bottom portion and a side surface of a concave portion formed using the gate film between the 1st gate electrode and the 3rd gate electrode by etching the hard mask film. The (c) is a step of forming a 2nd gate electrode of the 1st memory cell transistor on the 1st region, a 4th gate electrode of the 2nd memory cell transistor on the 2nd region, and a connection layer which connects the 2nd gate electrode and the 4th gate electrode under the 1st hard mask layer by etching the gate film.
    Type: Application
    Filed: June 18, 2007
    Publication date: December 27, 2007
    Inventors: Hideki Sugiyama, Hideki Hara
  • Publication number: 20070004722
    Abstract: The present invention relates to a 1,2,4-thiadiazole compound of the formula (I) represented by the formula (1): wherein R1? represents C3-C7 alkynyl and X represents C4-C7 straight alkylene optionally substituted with one to four of R2?, C4-C7 straight alkenylene optionally substituted with one to four of R2?, ethylene-oxy-ethylene optionally substituted with one to four of R4?, or ethylene-thio-ethylene optionally substituted with one to four of R4?, R2? represents a halogen atom, trifluoromethyl or C1-C4 alkyl, and R4 represents a fluorine atom or C1-C3 alkyl. The 1,2,4-thiadiazole compound has an excellent pests controlling activity, and can effectively control an pests such as insect pests, acarine pests and the like.
    Type: Application
    Filed: September 27, 2004
    Publication date: January 4, 2007
    Inventors: Hideki Hara, Daisuke Takaoka, Hajime Mizuno
  • Publication number: 20060011971
    Abstract: A nonvolatile semiconductor memory device has a substrate, a floating gate, a buried gate, a control gate, and source/drain regions. The substrate has a trench formed in a first direction. The floating gate is formed on a surface of the substrate outside the trench through a first gate insulating film. The buried gate is formed on a surface of the trench through a second gate insulating film. The control gate is formed to cover the floating gate through a third gate insulating film. The source/drain regions are formed in the substrate below the floating gate.
    Type: Application
    Filed: July 8, 2005
    Publication date: January 19, 2006
    Applicant: NEC Electronic Corporation
    Inventor: Hideki Hara
  • Patent number: 6924807
    Abstract: An apparatus for processing image data to produce an image for covering an image area of a display includes a plurality of graphics processors, each graphics processor being operable to render the image data into frame image data and to store the frame image data in a respective local frame buffer; a control processor operable to provide instructions to the plurality of graphics processors; and at least one merge unit operable to synchronously receive the frame image data from the respective local frame buffers and to synchronously produce combined frame image data based thereon.
    Type: Grant
    Filed: March 23, 2001
    Date of Patent: August 2, 2005
    Assignee: Sony Computer Entertainment Inc.
    Inventors: Hitoshi Ebihara, Kazumi Sato, Masakazu Mokuno, Hideki Hara
  • Patent number: 6919596
    Abstract: A lower electrode in a capacitive element area is formed on a field oxide film in self-alignment with trenches, so that the lower electrode and floating gate electrodes in a memory cell area can simultaneously be formed in one process. The lower electrode is surrounded by the trenches defined in the field oxide film. An upper electrode formed together with a control gate electrode in one process is disposed over the lower electrode with an insulating film, which is formed together with an intergate insulating film in the memory cell area in one process, interposed therebetween. With this arrangement, a semiconductor device having a capacitive element for use in a charge pump circuit or the like has its chip area prevented from being increased, allow the capacitive element to have a highly accurate capacitance, and can be manufactured in a reduced number of fabrication steps.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: July 19, 2005
    Assignee: NEC Electronics Corporation
    Inventors: Hideki Hara, Kazuhiko Sanada
  • Publication number: 20050080762
    Abstract: A file storage apparatus capable of restoring integrity of file management information even when a power supply abnormality occurs without lowering the write speed. When updating meta data stored in an HDD, log data for reconstructing the meta data after update from the meta data before update is written into a non-volatile RAM (NVRAM), then, after this writing is completed, the update is executed. Accordingly, even when the update use meta data temporarily stored in a cache memory is partially lost due to trouble such as a power supply abnormality and when update of the meta data of a hard disk is incomplete, the log data corresponding to the meta data for the update is held in the NVRAM, so it becomes possible to restore the integrity of the meta data on the hard disk by using this log data.
    Type: Application
    Filed: October 8, 2004
    Publication date: April 14, 2005
    Inventors: Katsuya Nakashima, Hideki Hara, Takashi Akai, Toshifumi Nomura, Kazumi Sato, Yukihisa Tsuneda, Toshiyuki Nishihara