Patents by Inventor Hideki Kitagawa
Hideki Kitagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11945729Abstract: A method for producing a nickel cobalt complex hydroxide includes first crystallization of supplying a solution containing Ni, Co and Mn, a complex ion forming agent and a basic solution separately and simultaneously to one reaction vessel to obtain nickel cobalt complex hydroxide particles, and a second crystallization of, after the first crystallization, further supplying a solution containing nickel, cobalt, and manganese, a solution of a complex ion forming agent, a basic solution, and a solution containing said element M separately and simultaneously to the reaction vessel to crystallize a complex hydroxide particles containing nickel, cobalt, manganese and said element M on the nickel cobalt complex hydroxide particles crystallizing a complex hydroxide particles comprising Ni, Co, Mn and the element M on the nickel cobalt complex hydroxide particles.Type: GrantFiled: December 3, 2021Date of Patent: April 2, 2024Assignee: NICHIA CORPORATIONInventors: Hideki Yoshida, Masato Sonoo, Takahiro Kitagawa
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Patent number: 11804498Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.Type: GrantFiled: May 21, 2020Date of Patent: October 31, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tatsuya Kawasaki, Tohru Daitoh, Hajime Imai, Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Teruyuki Ueda
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Patent number: 11790867Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: December 7, 2022Date of Patent: October 17, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20230305201Abstract: A reflection plate includes a substrate, an insulation film disposed on the substrate and including projection portions and recesses on an uneven surface, and a reflection film disposed on the uneven surface and having a surface that conforms to the uneven surface and reflecting light. The projection portions are arranged at intervals and are inclined with respect to a normal direction of a surface of the substrate. The recesses are between the projection portions that are adjacent to each other. The projection portions include a first projection portion, a second projection portion, and a third projection portion that are inclined in different directions.Type: ApplicationFiled: March 15, 2023Publication date: September 28, 2023Inventors: Yutaka SAWAYAMA, Yoshimasa CHIKAMA, Masamitsu YAMANAKA, Hideki KITAGAWA
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Publication number: 20230215876Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.Type: ApplicationFiled: March 9, 2023Publication date: July 6, 2023Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH
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Publication number: 20230178561Abstract: An active matrix substrate includes a substrate, a plurality of thin-film transistors, a plurality of pixel electrodes, and a first insulating layer. Each pixel electrode is formed from a transparent conducting material. Each thin-film transistor includes a gate electrode, a gate insulating layer, source and drain electrodes, and an oxide semiconductor layer. The oxide semiconductor layer includes a channel region, a source contact region, and a drain contact region. The source electrode has a stack structure including a source transparent conducting layer and a source metal layer. The drain electrode includes a drain transparent conducting layer. The drain transparent conducting layer is formed integrally with a corresponding one of the plurality of pixel electrodes.Type: ApplicationFiled: December 5, 2022Publication date: June 8, 2023Inventors: Hideki KITAGAWA, Yoshimasa CHIKAMA, Masamitsu YAMANAKA
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Patent number: 11637132Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.Type: GrantFiled: January 25, 2021Date of Patent: April 25, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Masahiko Suzuki, Tetsuo Kikuchi, Hideki Kitagawa, Setsuji Nishimiya, Kengo Hara, Hitoshi Takahata, Tohru Daitoh
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Publication number: 20230100273Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: December 7, 2022Publication date: March 30, 2023Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11551629Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: April 20, 2022Date of Patent: January 10, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11476282Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.Type: GrantFiled: August 4, 2020Date of Patent: October 18, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Yoshihito Hara, Tohru Daitoh, Hajime Imai, Masaki Maeda, Tatsuya Kawasaki, Hideki Kitagawa, Yoshiharu Hirata
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Publication number: 20220246105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: April 20, 2022Publication date: August 4, 2022Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11322105Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: August 13, 2021Date of Patent: May 3, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Patent number: 11302718Abstract: Each of pixel regions of an active matrix substrate (1002) includes: a lower insulating layer (5); an oxide semiconductor layer (7) that is arranged on the lower insulating layer and includes an active region (7a) of an oxide semiconductor TFT; an upper insulating layer (9) that is arranged on a portion of the oxide semiconductor layer so as not to be in contact with the lower insulating layer; an upper gate layer (10) that is arranged on the upper insulating layer and includes an upper gate electrode (10a) and one of a plurality of gate bus lines (GL); and a source electrode and a drain electrode, wherein: the oxide semiconductor layer 7 further includes an extension region (7e) that extends from the active region (7a) in a direction x different from a channel length direction y of the oxide semiconductor TFT as seen from a normal direction to the substrate; and the extension region (7e) is arranged on the substrate side of one of the plurality of gate bus lines (GL) with an upper insulating layer (9) interpType: GrantFiled: May 11, 2018Date of Patent: April 12, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Kengo Hara, Tohru Daitoh, Hajime Imai, Tetsuo Kikuchi, Hideki Kitagawa, Teruyuki Ueda, Masahiko Suzuki, Setsuji Nishimiya, Toshikatsu Itoh
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Patent number: 11215891Abstract: An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.Type: GrantFiled: May 21, 2020Date of Patent: January 4, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Yoshihito Hara, Masaki Maeda, Yoshiharu Hirata, Tatsuya Kawasaki, Teruyuki Ueda, Hajime Imai, Tohru Daitoh
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Publication number: 20210390920Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: ApplicationFiled: August 13, 2021Publication date: December 16, 2021Inventors: Tetsuo KIKUCHI, Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Patent number: 11189645Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: GrantFiled: March 26, 2018Date of Patent: November 30, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Tetsuo Kikuchi, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20210305280Abstract: There is provided a high-definition active matrix substrate while suppressing an occurrence of pixel defects. The active matrix substrate includes a first semiconductor film corresponding to one of two sub-pixels adjacent to each other in a row direction, a second semiconductor film corresponding to the other of two sub-pixels, a transistor using part of the first semiconductor film as a channel in the row direction, and a pixel electrode connected to a drain electrode of the transistor through a contact hole. In a plan view, a distance (dc) in the row direction from a drain electrode-side edge of the channel to a bottom surface of the contact hole is 0.15 or more times a sub-pixel pitch (dp) in the row direction.Type: ApplicationFiled: March 26, 2018Publication date: September 30, 2021Inventors: Hideki KITAGAWA, Hajime IMAI, Toshikatsu ITOH, Tetsuo KIKUCHI, Masahiko SUZUKI, Teruyuki UEDA, Kengo HARA, Setsuji NISHIMIYA, Tohru DAITOH
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Publication number: 20210294138Abstract: A pixel area in the active matrix substrate 100 includes a thin film transistor 101 that has an oxide semiconductor layer 7, an inorganic insulating layer 11 and an organic insulating layer 12 that cover a thin film transistor, a common electrode 15, a dielectric layer 17 that primarily contains silicon nitride, and a pixel electrode 19. The inorganic insulating layer has a multi-layered structure that includes a silicon oxide layer and a silicon nitride layer. A pixel electrode 10 is brought into contact with a drain electrode 9 within a pixel contact hole. The pixel contact hole is configured with a first opening portion, a second opening portion, and a third opening portion that are formed in the inorganic insulating layer 11, the organic insulating layer 12, and the dielectric layer 17, respectively. A flank surface of the first opening portion and a flank surface of the second opening portion are aligned.Type: ApplicationFiled: September 19, 2017Publication date: September 23, 2021Inventors: Hideki KITAGAWA, Tohru DAITOH, Hajime IMAI, Tetsuo KIKUCHI, Masahiko SUZUKI, Toshikatsu ITOH, Teruyuki UEDA, Setsuji NISHIMIYA, Kengo HARA
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Patent number: 11107429Abstract: According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.Type: GrantFiled: March 16, 2018Date of Patent: August 31, 2021Assignee: SHARP KABUSHIKI KAISHAInventors: Tetsuo Kikuchi, Hideki Kitagawa, Hajime Imai, Toshikatsu Itoh, Masahiko Suzuki, Teruyuki Ueda, Kengo Hara, Setsuji Nishimiya, Tohru Daitoh
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Publication number: 20210249445Abstract: An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.Type: ApplicationFiled: January 25, 2021Publication date: August 12, 2021Inventors: Masahiko SUZUKI, Tetsuo KIKUCHI, Hideki KITAGAWA, Setsuji NISHIMIYA, Kengo HARA, Hitoshi TAKAHATA, Tohru DAITOH