Abstract: An active matrix substrate includes TFTs, an interlayer insulating layer, a common electrode, a first dielectric layer, pixel electrodes, a second dielectric layer, and touch wirings, in which each of the pixel electrodes at least partially overlaps the common electrode via the first dielectric layer, so that an auxiliary capacitance including each of the pixel electrodes, the common electrode, and the first dielectric layer is formed, the touch sensor electrodes include a first electrode, the touch wirings include a first wiring and a second wiring in the touch sensor electrodes, the second wiring extends to the other electrode across the first electrode when viewed from a normal direction, and a portion of the second wiring overlaps the first electrode via the first and the second dielectric layers, so that a touch wiring capacitance including the second wiring, the first electrode, the first and the second dielectric layers is formed.

Abstract: An active matrix substrate includes: a source metal layer including a plurality of source bus lines; a lower insulating layer covering the source metal layer; a oxide semiconductor TFT including an oxide semiconductor layer provided on the lower insulating layer; an inter-layer insulating layer covering the oxide semiconductor TFT; a pixel electrode provided on the inter-layer insulating layer; a common electrode including a plurality of sub common electrodes each of which is capable of functioning as a touch sensor electrode; a gate metal layer including a plurality of gate bus lines and a gate electrode; a drain metal layer including the drain electrode; and a plurality of touch sensor lines included in the drain metal layer and each electrically connected to any one of the sub common electrodes.

Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semiconductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.

Abstract: An oxide semiconductor TFT (201) of an active matrix substrate includes an oxide semiconductor layer (107), an upper gate electrode (112) disposed on a part of the oxide semiconductor layer via a gate insulating layer, and a source electrode (113) and a drain electrode (114). As viewed from a normal direction of the substrate, the oxide semiconductor layer (107) includes a first portion (p1) that overlaps the upper gate electrode, and a second portion (p2) that is located between the first portion and the source contact region or drain contact region, such that the gate insulating layer does not cover the second portion. The upper gate electrode (112) has a multilayer structure including an alloy layer (112L) that is in contact with the gate insulating layer and a metal layer (112U) that is disposed on the alloy layer. The metal layer is made of a first metallic element M; the alloy layer is made of an alloy containing the first metallic element M; and the first metallic element M is Cu, Mo, or Cr.

Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.

Abstract: The present invention provides a thin-film transistor array substrate that prevents semiconductor layers of thin-film transistor elements from having step disconnection even when the frame width is reduced. The thin-film transistor array substrate of the present invention includes a thin-film transistor element in a pixel region and a terminal in a terminal region. The thin-film transistor array substrate sequentially includes a support, an insulating layer, a gate electrode, a gate insulating layer, and a semiconductor layer in a cross-sectional view of the pixel region. A region with the insulating layer encompasses a region with the semiconductor layer in a plan view of the pixel region. The thin-film transistor array substrate sequentially includes the support, a lead line extending from the terminal, and the insulating layer in a cross-sectional view of the terminal region.

Abstract: An active matrix substrate includes TFTs, an interlayer insulating layer, a common electrode, a first dielectric layer, pixel electrodes, a second dielectric layer, and touch wirings, in which each of the pixel electrodes at least partially overlaps the common electrode via the first dielectric layer, so that an auxiliary capacitance including each of the pixel electrodes, the common electrode, and the first dielectric layer is formed, the touch sensor electrodes include a first electrode, the touch wirings include a first wiring and a second wiring in the touch sensor electrodes, the second wiring extends to the other electrode across the first electrode when viewed from a normal direction, and a portion of the second wiring overlaps the first electrode via the first and the second dielectric layers, so that a touch wiring capacitance including the second wiring, the first electrode, the first and the second dielectric layers is formed.

Abstract: An active matrix substrate includes gate bus lines; source bus lines; a lower insulating layer; an oxide semiconductor TFT; and a pixel electrode, in which the oxide semiconductor TFT includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode, a source electrode, and a first ohmic conductive portion that is coupled to the oxide semiconductor layer and the source electrode, the lower insulating layer includes a source opening portion exposing at least a portion of the source electrode, the first ohmic conductive portion is disposed on the lower insulating layer and in the source opening portion and is in direct contact with at least the portion of the source electrode in the source opening portion, and the first region of the oxide semiconductor layer is in direct contact with an upper surface of the first ohmic conductive portion.

Abstract: A semiconductor device (100) includes a TFT (10) supported on a substrate (11), wherein the TFT (10) includes a gate electrode (12g), a gate insulating layer (14) that covers the gate electrode (12g), and an oxide semiconductor layer (16) that is formed on the gate insulating layer (14). The oxide semiconductor layer 16 has a layered structure including a first oxide semiconductor layer (16a) in contact with the gate insulating layer (14) and a second oxide semiconductor layer (16b) layered on the first oxide semiconductor layer (16a). The first oxide semiconductor layer (16a) and the second oxide semiconductor layer (16b) both include In, Ga and Zn; an In atomic ratio of the first oxide semiconductor layer (16a) is greater than a Zn atomic ratio thereof, and an In atomic ratio of the second oxide semi-conductor layer (16b) is smaller than a Zn atomic ratio thereof; and the oxide semiconductor layer (16) has a side surface of a forward tapered shape.

Abstract: An active matrix substrate includes: a source metal layer including a plurality of source bus lines; a lower insulating layer covering the source metal layer; a oxide semiconductor TFT including an oxide semiconductor layer provided on the lower insulating layer; an inter-layer insulating layer covering the oxide semiconductor TFT; a pixel electrode provided on the inter-layer insulating layer; a common electrode including a plurality of sub common electrodes each of which is capable of functioning as a touch sensor electrode; a gate metal layer including a plurality of gate bus lines and a gate electrode; a drain metal layer including the drain electrode; and a plurality of touch sensor lines included in the drain metal layer and each electrically connected to any one of the sub common electrodes.

Abstract: The present invention has an object to reduce the number of necessary masks to reduce manufacturing cost. A method of manufacturing a display device includes: forming electrodes or first lines; forming a first insulating film covering the electrodes or the first lines; forming a second insulating film covering the first insulating film; collectively forming first contact holes through the first insulating film and the second insulating film so as to expose parts of the electrodes or parts of the first lines; planarizing a surface of the second insulating film; and forming a first conductive layer to be connected from the surface of the second insulating film to the exposed parts of the electrodes or the exposed parts of the first lines via the first contact holes.

Abstract: An active matrix substrate includes: a substrate; lower bus lines and upper bus lines; a lower insulating layer positioned between the lower bus lines and the upper bus lines; an oxide semiconductor TFT that are disposed in each pixel region and have an oxide semiconductor layer disposed on the lower insulating layer; pixel electrodes disposed in each pixel region; and wiring connection units arranged in a non-display region. Each wiring connection unit includes: a lower conductive layer formed using the same conductive film as the lower bus lines; an insulating layer that extends on the lower conductive layer and includes the lower insulating layer. The lower bus lines and the lower conductive layer have a first laminated structure including a metal layer and a transparent conductive layer that covers an upper surface and a side surface of the metal layer.

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.

Abstract: An active matrix substrate according to an embodiment of the present invention includes a plurality of thin film transistors supported on a substrate and an inorganic insulating layer covering the plurality of thin film transistors. Each thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer, a source electrode, and a drain electrode. At least one of the gate insulating layer and the inorganic insulating layer is an insulating layer stack having a multilayer structure including a silicon oxide layer and a silicon nitride layer. The insulating layer stack further includes an intermediate layer disposed between the silicon oxide layer and the silicon nitride layer, the intermediate layer having a refractive index nC higher than a refractive index nA of the silicon oxide layer and lower than a refractive index nB of the silicon nitride layer.

Abstract: Provided is an active matrix substrate provided with a substrate (1), a peripheral circuit that includes a first oxide semiconductor thin-film transistor (TFT) (101), a plurality of second oxide semiconductor TFTs (102) disposed in a display area, and a first inorganic insulating layer (11) covering the plurality of second oxide semiconductor TFTs (102), the first oxide semiconductor TFT (101) having a lower gate electrode (3A), a gate insulating layer (4), an oxide semiconductor (5A) disposed so as to face the lower gate electrode with the gate insulating layer interposed therebetween, a source electrode (7A) and a drain electrode (8A), and an upper gate electrode (BG) disposed on the oxide semiconductor (5A) with an insulating layer that includes the first inorganic insulating layer (11) interposed therebetween, and furthermore having, on the upper gate electrode (BG), a second inorganic insulating layer (17) covering the first oxide semiconductor TFT (101).

Abstract: An active matrix substrate includes a gate metal layer including a plurality of gate bus lines, and a thin film transistor arranged in each pixel region, wherein: the thin film transistor includes a gate electrode, an oxide semiconductor layer arranged on the gate electrode with a gate insulating layer interposed therebetween, wherein the gate electrode is formed in the gate metal layer and is electrically connected to a corresponding one of the plurality of gate bus lines, the gate metal layer has a layered structure including a copper alloy layer and a copper layer arranged on the copper alloy layer, wherein the copper alloy layer is of a copper alloy including Cu and at least one additive metal element, wherein the additive metal element includes Al, and an Al content of the copper alloy is 2 at % or more and 8 at % or less.

Abstract: A semiconductor device (100A) is provided with: a gate electrode (3); an oxide semiconductor layer (5); a thin-film transistor (101) including a gate insulating layer (4), a source electrode (7S), and a drain electrode (7D); an inter-layer insulating layer (11) arranged so as to cover the thin-film transistor (101) and come into contact with a channel area (5c) of the thin-film transistor (101); and a transparent electroconductive layer (19) arranged on the inter-layer insulating layer (11), the source electrode (7S) and the drain electrode (7D) each having a copper layer (7a), and the device being further provided with a copper oxide film (8) arranged between the source and drain electrodes and the inter-layer insulating layer (11). The inter-layer insulating layer (11) covers the drain electrode (7D) with the copper oxide film (8) interposed therebetween.

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer, a gate electrode, a gate insulating layer, a source electrode, a drain electrode, the semiconductor layer includes a layered structure including a first oxide semiconductor layer including In and Zn, in which an atomic ratio of In with respect to all metallic elements included in the first oxide semiconductor layer is higher than an atomic ratio of Zn, a second oxide semiconductor layer including In and Zn, in which an atomic ratio of Zn with respect to all metallic elements included in the second oxide semiconductor layer is higher than an atomic ratio of In, and an intermediate oxide semiconductor layer arranged between the first oxide semiconductor layer and the second oxide semiconductor layer, and the first and second oxide semiconductor layers are crystalline oxide semiconductor layers, and the intermediate oxide semiconductor layer is an amorphous oxide semiconductor layer, and the first oxide semiconductor layer is

Abstract: A semiconductor device (100) of an embodiment of the present invention includes: a substrate (1); a plurality of TFTs (10) supported by the substrate; and a protecting layer (20) covering the plurality of TFTs. Each of the TFTs is a back channel etch type TFT which includes a gate electrode (2), a gate insulating layer (3), an oxide semiconductor layer (4), a source electrode (5) and a drain electrode (6). The gate electrode includes a tapered portion (TP) defined by a lateral surface (2s) which has a tapered shape. When viewed in a direction normal to a substrate surface, a periphery of the oxide semiconductor layer includes an edge (4e1, 4e2) which extends in a direction intersecting a channel width direction (DW) and which is more internal than an edge of the gate electrode in the channel width direction. The distance from the edge of the oxide semiconductor layer to an inside end of the tapered portion is not less than 1.5 ?m.

Abstract: A semiconductor device includes a substrate and a thin film transistor supported by the substrate. The thin film transistor includes a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and source and drain electrodes electrically connected to the oxide semiconductor layer. The gate insulating layer includes a first portion which is covered with the oxide semiconductor layer and a second portion which is adjacent to the first portion and which is not covered with any of the oxide semiconductor layer, the source electrode and the drain electrode. The second portion is smaller in thickness than the first portion, and the difference in thickness between the second portion and the first portion is more than 0 nm and not more than 50 nm.