Patents by Inventor Hideki Makiyama
Hideki Makiyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180219067Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: March 20, 2018Publication date: August 2, 2018Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Patent number: 10014385Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.Type: GrantFiled: September 27, 2017Date of Patent: July 3, 2018Assignee: Renesas Electronics CorporationInventor: Hideki Makiyama
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Patent number: 9978839Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: GrantFiled: June 21, 2017Date of Patent: May 22, 2018Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Patent number: 9960183Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.Type: GrantFiled: May 24, 2017Date of Patent: May 1, 2018Assignee: Renesas Electronics CorporationInventor: Hideki Makiyama
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Patent number: 9887301Abstract: Performances of a semiconductor device are improved. The semiconductor device has: a gate electrode formed on an SOI layer of an SOI substrate via a gate insulating film having a charge storage film therein; an n-type semiconductor region and a p-type semiconductor region respectively formed on SOI layers on both sides of the gate electrode. A memory cell MC serving as a non-volatile memory cell is formed of the gate insulating film, the gate electrode, the n-type semiconductor region and the p-type semiconductor region.Type: GrantFiled: July 3, 2016Date of Patent: February 6, 2018Assignee: Renesas Electric CorporationInventor: Hideki Makiyama
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Publication number: 20180019315Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.Type: ApplicationFiled: September 27, 2017Publication date: January 18, 2018Inventor: Hideki MAKIYAMA
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Publication number: 20170352687Abstract: A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film are laminated on a semiconductor substrate, and a device isolation region is embedded in a trench. The insulating film in a bulk region is removed; the semiconductor layer in the bulk region is removed; and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are thinned. An impurity is implanted into the semiconductor substrate in the SOI region, and thereafter the insulating film in the SOI region and the insulating layer in the bulk region are removed.Type: ApplicationFiled: May 24, 2017Publication date: December 7, 2017Applicant: Renesas Electronics CorporationInventor: Hideki MAKIYAMA
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Patent number: 9806165Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.Type: GrantFiled: November 24, 2016Date of Patent: October 31, 2017Assignee: Renesas Electronics CorporationInventor: Hideki Makiyama
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Publication number: 20170294513Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: June 21, 2017Publication date: October 12, 2017Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Patent number: 9773872Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: GrantFiled: September 29, 2016Date of Patent: September 26, 2017Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Publication number: 20170222013Abstract: The thickness of an insulating film, which will serve as an offset spacer film and is formed in an offset monitor region, is managed as the thickness of an offset spacer film formed over the side wall surface of a gate electrode of an SOTB transistor STR, etc. When the measured thickness is within the tolerance of a standard thickness, standard implantation energy and a standard dose amount are set. When the measured thickness is smaller than the standard thickness, implantation energy and a dose amount, which are respectively lower than the standard values thereof, are set. When the measured thickness is larger than the standard thickness, implantation energy and a dose amount, which are respectively higher than the standard values thereof, are set.Type: ApplicationFiled: November 24, 2016Publication date: August 3, 2017Inventor: Hideki MAKIYAMA
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Publication number: 20170062624Abstract: Performances of a semiconductor device are improved. The semiconductor device has: a gate electrode formed on an SOI layer of an SOI substrate via a gate insulating film having a charge storage film therein; an n-type semiconductor region and a p-type semiconductor region respectively formed on SOI layers on both sides of the gate electrode. A memory cell MC serving as a non-volatile memory cell is formed of the gate insulating film, the gate electrode, the n-type semiconductor region and the p-type semiconductor region.Type: ApplicationFiled: July 3, 2016Publication date: March 2, 2017Inventor: Hideki MAKIYAMA
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Publication number: 20170018611Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: ApplicationFiled: September 29, 2016Publication date: January 19, 2017Inventors: Yoshiki YAMAMOTO, Hideki MAKIYAMA, Toshiaki IWAMATSU, Takaaki TSUNOMURA
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Patent number: 9484271Abstract: Characteristics of a semiconductor device are improved. A semiconductor device of the present invention includes: (a) a MISFET arranged in an active region formed of a semiconductor region surrounded by an element isolation region; and (b) an insulating layer arranged below the active region. Further, the semiconductor device includes: (c) a p-type semiconductor region arranged below the active region so as to interpose the insulating layer; and (d) an n-type semiconductor region whose conductivity type is opposite to the p-type, arranged below the p-type semiconductor region. And, the p-type semiconductor region includes a connection region extending from below the insulating layer, and the p-type semiconductor region and a gate electrode of the MISFET are connected to each other by a shared plug which is an integrally-formed conductive film extending from above the gate electrode to above the connection region.Type: GrantFiled: April 15, 2015Date of Patent: November 1, 2016Assignee: Renesas Electronics CorporationInventors: Katsuyuki Horita, Toshiaki Iwamatsu, Hideki Makiyama, Yoshiki Yamamoto
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Patent number: 9484433Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.Type: GrantFiled: November 2, 2015Date of Patent: November 1, 2016Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Patent number: 9484456Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.Type: GrantFiled: July 18, 2015Date of Patent: November 1, 2016Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Toshiaki Iwamatsu, Takaaki Tsunomura
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Patent number: 9460936Abstract: The semiconductor device has a gate electrode GE formed on a substrate via a gate insulating film GI and a source/drain semiconductor layer EP1 formed on the substrate. The upper surface of the semiconductor layer EP1 is positioned higher than the upper surface of the substrate straight below the gate electrode GE. And, end parts of the gate electrode GE in a gate length direction are positioned on the semiconductor layer EP1.Type: GrantFiled: September 16, 2015Date of Patent: October 4, 2016Assignee: Renesas Electronics CorporationInventors: Yoshiki Yamamoto, Hideki Makiyama, Takaaki Tsunomura, Toshiaki Iwamatsu
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Patent number: 9455273Abstract: In a semiconductor device having an SRAM memory cell, its reliability is improved. In the semiconductor device having the SRAM memory cell, electrically-independent four semiconductor regions functioning as hack gates are provided below two load transistors and two driver transistors, so that threshold voltages for the load transistors and driver transistors are controlled. And, the two n-type semiconductor regions provided below the two load transistors are electrically isolated from each other by a p-type semiconductor region.Type: GrantFiled: October 22, 2015Date of Patent: September 27, 2016Assignee: Renesas Electronics CorporationInventor: Hideki Makiyama
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Publication number: 20160181147Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.Type: ApplicationFiled: February 26, 2016Publication date: June 23, 2016Inventors: Jiro YUGAMI, Toshiaki IWAMATSU, Katsuyuki HORITA, Hideki MAKIYAMA, Yasuo INOUE, Yoshiki YAMAMOTO
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Patent number: 9343527Abstract: A first MISFET which is a semiconductor element is formed on an SOI substrate. The SOI substrate includes a supporting substrate which is a base, BOX layer which is an insulating layer formed on a main surface (surface) of the supporting substrate, that is, a buried oxide film; and an SOI layer which is a semiconductor layer formed on the BOX layer. The first MISFET as a semiconductor element is formed to the SOI layer. In an isolation region, an isolation groove is formed penetrating though the SOI layer and the BOX layer so that a bottom surface of the groove is positioned in the middle of a thickness of the supporting substrate. An isolation film is buried in the isolation groove being formed. Then, an oxidation resistant film is interposed between the BOX layer and the isolation film.Type: GrantFiled: December 2, 2012Date of Patent: May 17, 2016Assignee: Renesas Electronics CorporationInventors: Jiro Yugami, Toshiaki Iwamatsu, Katsuyuki Horita, Hideki Makiyama, Yasuo Inoue, Yoshiki Yamamoto