Abstract: Occurrence of short-channel characteristics and parasitic capacitance of a MOSFET on a SOI substrate is prevented. A sidewall having a stacked structure obtained by sequentially stacking a silicon oxide film and a nitride film is formed on a side wall of a gate electrode on the SOI substrate. Subsequently, after an epitaxial layer is formed beside the gate electrode, and then, the nitride film is removed. Then, an impurity is implanted into an upper surface of the semiconductor substrate with using the gate electrode and the epitaxial layer as a mask, so that a halo region is formed in only a region of the upper surface of the semiconductor substrate which is right below a vicinity of both ends of the gate electrode.

Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

Abstract: A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

Abstract: Improvements are achieved in the characteristics of a semiconductor device including SRAM memory cells. Under an active region in which an access transistor forming an SRAM is disposed, a p-type semiconductor region is disposed via an insulating layer such that the bottom portion and side portions thereof come in contact with an n-type semiconductor region. Thus, the p-type semiconductor region is pn-isolated from the n-type semiconductor region, and the gate electrode of the access transistor is coupled to the p-type semiconductor region. The coupling is achieved by a shared plug which is an indiscrete conductive film extending from over the gate electrode of the access transistor to over the p-type semiconductor region. As a result, when the access transistor is in an ON state, a potential in the p-type semiconductor region serving as a back gate simultaneously increases to allow an increase in an ON current for the transistor.

Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.

Abstract: The semiconductor integrated circuit device has a hybrid substrate structure which includes both of an SOI structure and a bulk structure on the side of the device plane of a semiconductor substrate. In the device, the height of a gate electrode of an SOI type MISFET is higher than that of a gate electrode of a bulk type MISFET with respect to the device plane.

Abstract: A semiconductor device with an SRAM memory cell having improved characteristics. Below an active region in which a driver transistor including a SRAM is placed, an n type back gate region surrounded by an element isolation region is provided via an insulating layer. It is coupled to the gate electrode of the driver transistor. A p well region is provided below the n type back gate region and at least partially extends to a position deeper than the element isolation region. It is fixed at a grounding potential. Such a configuration makes it possible to control the threshold potential of the transistor to be high when the transistor is ON and to be low when the transistor is OFF; and control so as not to apply a forward bias to the PN junction between the p well region and the n type back gate region.

Abstract: Logic transistors (MOSFETs, MISFETs) in core portions of integrated circuits can be microminiaturized by scaling operating voltage as their generation advances. However, since transistors (MOSFETs, MISFETs) in high-breakdown voltage portions operate on relatively high power supply voltage, it is difficult to reduce their size. Similarly, electrostatic discharge (ESD) protection circuits in power supply cells protect the elements in a semiconductor integrated circuit against static electricity (foreign surge); therefore, they are indispensably required to be high in breakdown voltage and call for a large area for dissipating electric charges. To microminiaturize integrated circuits, therefore, a transistor structure that enables microminiaturization is indispensable.

Abstract: In shipping a computer ordered by selecting parts on a sales site offered by a sales management server, a shortcut link incorporating part codes as parameters of a URL on the support information site offered by a FAQ server, is set on a desktop screen of the computer. On the other hand, part codes, questions probable to arouse concerning the parts and answers thereto are registered as data in a database. When the short-cut link is selected on the desktop screen of the computer, the FAQ server accessible via a web management server obtains part codes from the URL, and sends the data picked up from the database by using the part codes, as a FAQ page, to the side of the user.

Abstract: A user's computer 1 is a computer that a user purchases from a manufacturer. The computer 1, a host computer 3 for the manufacturer that sold the computer 1 to provides a support service, and a terminal unit 4 operated by a person in charge of support are connected to a network 2. A storage unit 5 in the host computer 3 stores a database for user support. This database includes the specifications 11 of computer at the time it is purchased, installed software 12, information 13 on the condition of a trouble that occurred, information 14 on a troubleshooting measure, information 15 on the content of a repair request, and information on the progress of repair processing. All of information which is usable for computer support can be viewed by a user and a service person, and a prompt and appropriate support can be performed. Also, the condition of repair can be checked in real time.